Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Public

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6.2. LVDS SERDES Source-Synchronous Timing Budget

The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead of the clock-to-output setup times. High-speed differential data transmission requires the use of timing parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.