Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Public
Document Table of Contents
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6.1.2. FPGA Timing Analysis

When you generate the LVDS SERDES IP, the IP generates the SERDES hardware clock settings and the core clock for IP timing analysis.
Table 34.  Clocks for the Transmitter and Receiver in Non-DPA and DPA-FIFO ModesBecause the frequency of LVDS fast clock is higher than the user core clock by the serialization factor, the IP also creates multicycle path constraints for proper timing analysis at the SERDES–core interface.
Clock Clock Name
Core clock

<lvds_instance_name>|cpa_clk

LVDS fast clock
  • Receiver— <lvds_instance_name>|p2c_fa_div_clk_<byte_num>
  • Transmitter— <lvds_instance_name>|c2p_fa_div_clk_<byte_num>
Table 35.  Clock for the Receiver in Soft-CDR Mode
Clock Clock Name
Core clock

<lvds_instance_name>|cpa_clk

DPA fast clock

<lvds_instance_name>|dpa_core_clk_<byte_num>_<pin_num>