Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Document Table of Contents LVDS SERDES Intel® FPGA IP PLL Settings

Table 17.  PLL Settings Tab
Parameter Value Description
Use external PLL
  • On
  • Off

Turn on to use an external PLL:

  • The IP does not instantiate a local PLL.
  • The IP creates a series of clock connections with the "ext" prefix. Connect these ports to an externally generated PLL.
  • For details about how to configure the external PLL, refer to the Clock Resource Summary tab of the parameter editor.

This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration.

Desired inclock frequency

Specifies the inclock frequency in MHz.

Actual inclock frequency

Displays the closest inclock frequency to the desired frequency that can source the interface.

FPGA/PLL speed grade

Displays the FPGA/PLL speed grade, which determines the operation range of the PLL.