Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Document Table of Contents

1.1. LVDS SERDES Usage Modes

You can use the M-Series LVDS SERDES through the LVDS SERDES Intel® FPGA IP. The LVDS SERDES IP supports four SERDES functional modes.
Table 1.  Summary of the M-Series LVDS SERDES Usage ModesAll usage modes in this table support SERDES factors of 4 and 8.
Functional Mode Description



  • The SERDES block acts as a serializer.
  • A PLL generates these signals:
    • fast_clock
    • load_enable

Non-DPA receiver

(RX Non-DPA)

  • The SERDES block acts as a deserializer that bypasses the DPA and DPA-FIFO.
  • A PLL generates the fast_clock signal.
  • The SERDES captures the incoming data at the bit slip with the fast_clock signal. Therefore, you must ensure the correct clock–data alignment.

DPA-FIFO receiver


  • The SERDES block acts as a deserializer that uses the DPA block.
  • The DPA block uses a set of eight DPA clocks to select the optimal phase for sampling data.
    • The DPA clocks run at the fast_clock frequency with each clock phase-shifted 45° apart.
    • The DPA-FIFO, a circular buffer, samples the incoming data with the selected DPA clock and forwards the data to LVDS clock domain.
    • The bit slip circuitry then samples the data and inserts latencies to realign the data to match the desired word boundary of the deserialized data.

Soft-CDR receiver

(RX Soft-CDR)

  • The LVDS SERDES IP forwards these clocks:
    • The optimal DPA clock (DPACLK) into the LVDS clock domain as the fast_clock signal.
    • The rx_divfwdclk, produced by the local clock generator, to the device core.
  • Each bank has only 12 soft-CDR channels available. Refer to the device pin-out files to determine which pin pairs can support soft-CDR channels in each bank.