Intel Agilex® 7 LVDS SERDES User Guide: M-Series

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ID 768615
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 M-Series LVDS SERDES Overview 2. Intel Agilex® 7 M-Series LVDS SERDES Architecture 3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter 4. Intel Agilex® 7 M-Series LVDS SERDES Receiver 5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide 6. Intel Agilex® 7 M-Series LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines 9. Intel Agilex® 7 M-Series LVDS SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series 11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
1. Intel Agilex® 7 M-Series LVDS SERDES Overview x
1.1. LVDS SERDES Usage Modes
2. Intel Agilex® 7 M-Series LVDS SERDES Architecture x
2.1. Intel Agilex® 7 M-Series GPIO-B Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations 3.2.2. Differential I/O Bit Position
3.3. Clocking the Differential Transmitters x
3.3.1. Transmitter Output Clock Parameters Settings
3.3.1. Transmitter Output Clock Parameters Settings x
3.3.1.1. Edge-Aligned tx_outclock to tx_out
4. Intel Agilex® 7 M-Series LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings
4.2.1. Receiver Input Clock Parameters Settings x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES Intel® FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES Intel® FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES Intel® FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Planning the LVDS Interface 5.1.5. Generating the LVDS SERDES Intel® FPGA IP 5.1.6. LVDS SERDES Intel® FPGA IP Parameter Settings 5.1.7. LVDS SERDES Intel® FPGA IP Signals
5.1.5. Generating the LVDS SERDES Intel® FPGA IP x
5.1.5.1. Intel® FPGA IP Generation Output
5.1.6. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings 5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings x
5.1.6.2.1. GPIO-B Pin Index Number and Respective Channel Pin Selection 5.1.6.2.2. Placing Channel Bytes in I/O Lanes 5.1.6.2.3. Locating the I/O Lane and Channel Pin through the Interface Planner
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment
5.3.4. Word Boundaries Alignment x
5.3.4.1. Aligning Word Boundaries
6. Intel Agilex® 7 M-Series LVDS SERDES Timing x
6.1. LVDS SERDES Intel® FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES Intel® FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES Intel® FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example
8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS Transmitters and Receivers in the Same GPIO-B Sub-Bank 8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs 8.7. VCCIO_PIO Power Scheme for LVDS SERDES
8.3. Pin Placement for Differential Channels x
8.3.1. I/O PLLs Driving LVDS Transmitter and Receiver Channels 8.3.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank
1. Intel Agilex® 7 M-Series LVDS SERDES Overview
2. Intel Agilex® 7 M-Series LVDS SERDES Architecture
3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 M-Series LVDS SERDES Receiver
5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide
6. Intel Agilex® 7 M-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines
9. Intel Agilex® 7 M-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series

8.3.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank

If you use true differential I/O standards and single-ended I/O standards in the same or adjacent GPIO-B banks, adhere to the following placement guidelines. These restrictions do not apply to differential reference clock that feeds directly into the PLL reference clock ports.
  • Do not place true differential and toggling single-ended I/O standards in the combinations of locations listed in the following tables.
  • From version 24.1, the Intel® Quartus® Prime software issues the following errors:
    • Compilation error—violation of the same bank placement restriction.
    • Critical warning—assignment of true differential I/O standards to pin pairs with the following pin index numbers: 0 and 1, 6 and 7, 88 and 89, and 94 and 95.
Table 37.  Restricted Pin Placement Combinations for True Differential and Single-Ended I/O Standards in the Same GPIO-B Bank

This table lists the combinations of pins and I/O standards not allowed in the same GPIO-B bank. Examples:

  • If you place a true differential I/O standard in pin pair 10 and 11, do not place single-ended I/O standards in pins 9 or 18.
  • If you place a single-ended I/O standard in pin 57 or 66, do not place a true differential I/O standard in pin pair 58 and 59.
Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number)
True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin
0 and 1 2 24 and 25 17, 26 48 and 49 41, 50 72 and 73 65, 74
2 and 3 1, 4 26 and 27 25, 28 50 and 51 49, 52 74 and 75 73, 76
4 and 5 3, 12 28 and 29 27, 36 52 and 53 51, 60 76 and 77 75, 84
6 and 7 8 30 and 31 23, 32 54 and 55 47, 56 78 and 79 71, 80
8 and 9 7, 10 32 and 33 31, 34 56 and 57 55, 58 80 and 81 79. 82
10 and 11 9, 18 34 and 35 33, 42 58 and 59 57, 66 82 and 83 81, 90
12 and 13 5, 14 36 and 37 29, 38 60 and 61 53, 62 84 and 85 77, 86
14 and 15 13, 16 38 and 39 37, 40 62 and 63 61, 64 86 and 87 85, 88
16 and 17 15, 24 40 and 41 39, 48 64 and 65 63, 72 88 and 89 87
18 and 19 11, 20 42 and 43 35, 44 66 and 67 59, 68 90 and 91 83, 92
20 and 21 19, 22 44 and 45 43, 46 68 and 69 67, 70 92 and 93 91, 94
22 and 23 21, 30 46 and 47 45, 54 70 and 71 69, 78 94 and 95 93
Table 38.  Restricted Pin Placement Combinations for True Differential and Single-Ended I/O Standards in Adjacent GPIO-B Banks

This table lists the combinations of pins and I/O standards not allowed in adjacent GPIO-B banks. Examples:

  • If you place a true differential I/O standard in pin pair 6 and 7 of bank 3B, do not place single-ended I/O standards in pin 95 of bank 3A.
  • If you place a single-ended I/O standard in pin 0 of bank 2C, do not place a true differential I/O standard in pin pair 88 and 89 of bank 2D.
Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number)
True Differential Single-Ended True Differential Single-Ended
Bank Pin Pair Bank Pin Bank Pin Pair Bank Pin
3A 88 and 89 3B 0 2A 88 and 89 2B 89
94 and 95 6 94 and 95 95
3B 0 and 1 3A 89 2B 0 and 1 2C 89
6 and 7 95 6 and 7 95
88 and 89 3C 89 88 and 89 2A 89
94 and 95 95 94 and 95 95
3C 0 and 1 3D 89 2C 0 and 1 2D 89
6 and 7 95 6 and 7 95
88 and 89 3B 89 88 and 89 2B 0
94 and 95 95 94 and 95 6
3D 88 and 89 3C 0 2D 88 and 89 2C 0
94 and 95 6 94 and 95 6

Refer to the related information for the figure showing the locations of the GPIO-B banks.

Related Information
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