Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Document Table of Contents LVDS SERDES Intel® FPGA IP Transmitter Settings

The parameter options in the Transmitter Settings tab are available if Number of TX channels in the General Settings tab is not 0.
Table 21.  Transmitter Settings Tab
Parameter Value Description
Enable tx_outclock port
  • On
  • Off

Turn on to expose the tx_outclock port.

Default is On.

  • The tx_outclock port frequency depends on the setting for the Tx_outclock division factor parameter.
  • The phases of the tx_outclock_p and tx_outclock_n ports depend on the Desired tx_outclock phase shift parameter.

Turning on this parameter reduces the maximum number of channels per transmitter interface by one channel.

Desired tx_outclock phase shift (degrees)
  • 0
  • 360
  • 720

Specifies the phase relationship between the outclock and outgoing serial data in degrees of the LVDS fast clock.

Default is 0.

Actual tx_outclock phase shift (degrees)

Depends on the Desired tx_outclock phase shift (degrees) input. Refer to related information.

Displays the closest achievable tx_outclock phase shift to the desired tx_outclock phase shift.

Tx_outclock division factor Depends on the SERDES factor. Specifies the ratio of the fast clock frequency to the outclock frequency. For example, the maximum number of serial transitions per outclock cycle.