Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Document Table of Contents

8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs

If you use the LVDS SERDES Intel® FPGA IP in an I/O lane, you can use remaining pins of the lane only for the GPIO Intel® FPGA IP. You cannot mix the LVDS SERDES IP with the PHY Lite for Parallel Interfaces Intel® FPGA IP or the External Memory Interfaces (EMIF) IP in the same I/O lane.