Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Document Table of Contents

2. Intel Agilex® 7 M-Series LVDS SERDES Architecture

Each GPIO-B bank in M-Series devices consists of two sub-banks. Each sub-bank contains its own VCCIO_PIO and PLL. Each LVDS SERDES pair has its own dynamic phase alignment (DPA) and SERDES circuitry blocks.

You can configure each SERDES channel as a transmitter or a receiver.

Table 2.  Differential Pairs and Channel Mode Support in Each Bank and Sub-BankThis table lists the number of SERDES channels supported. Refer to the device pin-out files for the exact location of the SERDES and Soft-CDR pins.
Total Transmitter or Receiver Pairs Per Bank Channel Mode Maximum Pairs Per Sub-Bank

Top Index Sub-Bank

Bottom Index Sub-Bank


Transmitter 24 24
DPA 24 24
Non-DPA 24 24
Soft-CDR 4 8
2 One LVDS SERDES pair is used for the reference clock.