Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Document Table of Contents

3.1. LVDS SERDES Transmitter Blocks

In the M-Series LVDS SERDES transmitter, the serializer receives up to 8 bits 0 wide parallel data from the FPGA fabric.
Figure 3. LVDS SERDES Transmitter

  • The serializer clocks the data into the registers and serializes the data using a multiplexer.
  • The I/O PLL that drives the data to the differential buffer clocks the shift registers.
  • The multiplexer transmits the MSB of the parallel data first.
Note: The PLL that drives the SERDES channel must operate in integer PLL mode.