Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Public
Document Table of Contents
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1. Intel Agilex® 7 M-Series LVDS SERDES Overview

Updated for:
Intel® Quartus® Prime Design Suite 23.4
The Intel Agilex® 7 M-Series I/O system includes three types of I/O interfaces: general purpose I/Os (GPIO-B), Secure Device Manager (SDM) I/O, and Hard Processor System (HPS) I/O. Each I/O interface caters to different interfacing requirements.

M-Series devices support LVDS serializer/deserializer (SERDES) through True Differential Signaling and SLVS-400 I/O standards in the GPIO-B banks. The true differential I/Os are capable of supporting LVDS interfaces, including subsets such as:

  • RSDS
  • Mini-LVDS
  • SLVS
  • Any differential I/O standards using equivalent electrical specifications

M-Series devices support SERDES in all GPIO-B banks with the following features:

  • Configurable transmitter or receiver on all I/O pins
  • Serialize and deserialize functions up to 1.6 Gbps.
  • Clock data recovery (CDR) function on specific differential channel
  • Configurable 100 Ω differential on-chip termination (OCT RD)
  • Serializer or deserializer factors of 4 and 81
  • I/O standards support for the LVDS SERDES:
    • Transmitter—True Differential Signaling I/O standard at 1.3 V
    • Receiver:
      • DPA mode—True Differential Signaling and SLVS-400 I/O standards
      • Non-DPA mode—True Differential Signaling I/O standard only
1 Serialization factor of 8 is available only in M-Series FPGAs production devices.