Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 12/04/2023
Document Table of Contents LVDS SERDES Intel® FPGA IP General Settings

Table 12.  General Settings Tab
Parameter Value Description
Number of RX channels
  • RX Non-DPA—0 to 47
  • RX DPA-FIFO—0 to 47
  • RX Soft-CDR—0 to 12

Specifies the number of receiver channels in the interface.

Default is 1.

Place the refclk pin on the same I/O bank as the receiver.

Number of TX channels 0 to 47

Specifies the number of transmitter channels in the interface.

RX functional mode
  • RX Non-DPA
  • RX Soft-CDR

Specifies the functional mode of the receiver interface.

Default is RX Non-DPA.

These options are not available if Number of RX channels is 0.

Data rate
  • RX only—600.0 to 1600.0
  • TX only, or RX and TX—600.0 to 1580.0

Specifies the data rate (in Mbps) of a single serial channel.

Default is 800.0.

SERDES factor
  • RX—4 or 8
  • TX—4

Select the rate of serialization and deserialization for the LVDS interface.

Default is 4.

Note: Serialization factor of 8 is available only in M-Series FPGAs production devices.
I/O Standard
  • True Differential Signaling 1.3V
  • True Differential Signaling 1.2V
  • True Differential Signaling 1.1V
  • True Differential Signaling 1.05V
  • SLVS 1.2V
  • SLVS 1.1V
Select the I/O standard of the LVDS interface.