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1. Answers to Top FAQs
2. Signal Integrity Analysis with Third-Party Tools
3. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
4. Siemens EDA PCB Design Tools Support
5. Cadence Board Design Tools Support
6. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides
2.4.1. IBIS Model Access and Customization Flows
2.4.2. Elements of an IBIS Model
2.4.3. Customizing IBIS Models
2.4.4. Design Simulation Using the Siemens EDA HyperLynx* Software
2.4.5. Configuring LineSim to Use Intel IBIS Models
2.4.6. Integrating Intel IBIS Models into LineSim Simulations
2.4.7. Running and Interpreting LineSim Simulations
2.4.3.1. Customizing Downloaded IBIS Models for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices
2.4.3.2. Generate Custom IBIS Models with the EDA Netlist Writer GUI for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices
2.4.3.3. Customizing IBIS Model Files for Intel Agilex® 7 Devices
2.5.1. Supported Devices and Signaling
2.5.2. Accessing HSPICE Simulation Kits
2.5.3. The Double Counting Problem in HSPICE Simulations
2.5.4. HSPICE Writer Tool Flow
2.5.5. Running an HSPICE Simulation
2.5.6. Interpreting the Results of an Output Simulation
2.5.7. Interpreting the Results of an Input Simulation
2.5.8. Viewing and Interpreting Tabular Simulation Results
2.5.9. Viewing Graphical Simulation Results
2.5.10. Making Design Adjustments Based on HSPICE Simulations
2.5.11. Sample Input for I/O HSPICE Simulation Deck
2.5.12. Sample Output for I/O HSPICE Simulation Deck
2.5.13. Advanced Topics
2.5.4.1. Applying I/O Assignments
2.5.4.2. Enabling HSPICE Writer
2.5.4.3. Enabling HSPICE Writer Using Assignments
2.5.4.4. Naming Conventions for HSPICE Files
2.5.4.5. Invoking HSPICE Writer
2.5.4.6. Invoking HSPICE Writer from the Command Line
2.5.4.7. Customizing Automatically Generated HSPICE Decks
2.5.12.1. Header Comment
2.5.12.2. Simulation Conditions
2.5.12.3. Simulation Options
2.5.12.4. Constant Definition
2.5.12.5. I/O Buffer Netlist
2.5.12.6. Drive Strength
2.5.12.7. Slew Rate and Delay Chain
2.5.12.8. I/O Buffer Instantiation
2.5.12.9. Board and Trace Termination
2.5.12.10. Double-Counting Compensation Circuitry
2.5.12.11. Simulation Analysis
3.1. Reviewing Intel® Quartus® Prime Software Settings
3.2. Reviewing Device Pin-Out Information in the Fitter Report
3.3. Reviewing Compilation Error and Warning Messages
3.4. Using Additional Intel® Quartus® Prime Software Features
3.5. Using Additional Intel® Quartus® Prime Software Tools
3.6. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software Revision History
5.1. Cadence PCB Design Tools Support
5.2. Product Comparison
5.3. FPGA-to-PCB Design Flow
5.4. Setting Up the Intel® Quartus® Prime Software
5.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software
5.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software
5.7. Cadence Board Design Tools Support Revision History
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2.1. Signal Integrity Analysis with Third-Party Tools
With the ever-increasing operating speed of interfaces in traditional FPGA design, the timing and signal integrity margins between the FPGA and other devices on the board must be within specification and tolerance before building a PCB.
If the board trace design is poor, or the route is too heavily loaded, noise in the signal can cause data corruption, while overshoot and undershoot can potentially damage input buffers over time.
As FPGA devices are used in high-speed applications, signal integrity and timing margin between the FPGA and other devices on the PCB are important for proper system operation. To avoid time-consuming and costly board respins, you must simulate the topology and routing of critical signals. You must accurately model the high-speed interfaces available on FPGA devices.
The Intel® Quartus® Prime software provides methodologies, resources, and tools to ensure good signal integrity and timing margin between Intel® FPGA devices and other components on the board. Three types of analysis are possible with the Intel® Quartus® Prime software:
- I/O timing with a default or user-specified capacitive load and no signal integrity analysis (default)
- The Intel® Quartus® Prime Enable Advanced I/O Timing option utilizing a user-defined board trace model to produce enhanced timing reports from accurate “board-aware” simulation models
- Full board routing simulation in third-party tools using Intel-provided or generated Input/Output Buffer Information Specification (IBIS) or HSPICE I/O models
I/O timing using a specified capacitive test load requires no special configuration other than setting the size of the load. The Intel® Quartus® Prime Timing Analyzer generates I/O timing reports based only on point-to-point delays within the I/O buffer. The Timing Analyzer assumes the presence of the capacitive test load without specifying any other details about the board. The default size of the load derives from the I/O standard that you select for the pin. Timing analysis measures to the FPGA pin without signal integrity analysis details.
The Enable Advanced I/O Timing option expands the details in I/O timing reports by taking board topology and termination components into account. The timing analysis accounts for a complete point-to-point board trace model. The Timing Analyzer reports timing and signal integrity metrics between the I/O buffer and the defined far end load.
The signal integrity information in this chapter refers to board-level signal integrity based on I/O buffer configuration and board parameters, not simultaneous switching noise (SSN).1 SSN is a product of multiple output drivers switching at the same time, causing an overall drop in the voltage of the chip’s power supply. This condition can cause temporary glitches in the specified level of ground or VCC for the device.
This chapter provides FPGA and board designers with the concepts and steps necessary to perform signal integrity simulation and adjust designs to improve board-level timing and signal integrity. This chapter also includes information about how to obtain and customize simulation models, and how to use those models in simulation software.
1 Also known as ground bounce or VCC sag.