Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 8/01/2023

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Document Table of Contents

2.1. Signal Integrity Analysis with Third-Party Tools

With the ever-increasing operating speed of interfaces in traditional FPGA design, the timing and signal integrity margins between the FPGA and other devices on the board must be within specification and tolerance before building a PCB.

If the board trace design is poor, or the route is too heavily loaded, noise in the signal can cause data corruption, while overshoot and undershoot can potentially damage input buffers over time.

As FPGA devices are used in high-speed applications, signal integrity and timing margin between the FPGA and other devices on the PCB are important for proper system operation. To avoid time-consuming and costly board respins, you must simulate the topology and routing of critical signals. You must accurately model the high-speed interfaces available on FPGA devices.

The Intel® Quartus® Prime software provides methodologies, resources, and tools to ensure good signal integrity and timing margin between Intel® FPGA devices and other components on the board. Three types of analysis are possible with the Intel® Quartus® Prime software:

  • I/O timing with a default or user-specified capacitive load and no signal integrity analysis (default)
  • The Intel® Quartus® Prime Enable Advanced I/O Timing option utilizing a user-defined board trace model to produce enhanced timing reports from accurate “board-aware” simulation models
  • Full board routing simulation in third-party tools using Intel-provided or generated Input/Output Buffer Information Specification (IBIS) or HSPICE I/O models

I/O timing using a specified capacitive test load requires no special configuration other than setting the size of the load. The Intel® Quartus® Prime Timing Analyzer generates I/O timing reports based only on point-to-point delays within the I/O buffer. The Timing Analyzer assumes the presence of the capacitive test load without specifying any other details about the board. The default size of the load derives from the I/O standard that you select for the pin. Timing analysis measures to the FPGA pin without signal integrity analysis details.

The Enable Advanced I/O Timing option expands the details in I/O timing reports by taking board topology and termination components into account. The timing analysis accounts for a complete point-to-point board trace model. The Timing Analyzer reports timing and signal integrity metrics between the I/O buffer and the defined far end load.

The signal integrity information in this chapter refers to board-level signal integrity based on I/O buffer configuration and board parameters, not simultaneous switching noise (SSN).1 SSN is a product of multiple output drivers switching at the same time, causing an overall drop in the voltage of the chip’s power supply. This condition can cause temporary glitches in the specified level of ground or VCC for the device.

This chapter provides FPGA and board designers with the concepts and steps necessary to perform signal integrity simulation and adjust designs to improve board-level timing and signal integrity. This chapter also includes information about how to obtain and customize simulation models, and how to use those models in simulation software.

1 Also known as ground bounce or VCC sag.