Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 8/01/2023
Document Table of Contents Constant Definition

The constant definition block of the output simulation SPICE deck instantiates the voltage sources that controls the configuration modes of the I/O buffer.

Constant Definition Block

* Constant Definition
voeb oeb 0 0 * Set to 0 to enable buffer output
vopdrain opdrain 0 0 * Set to vc to enable open drain
vrambh rambh 0 0 * Set to vc to enable bus hold
vrpullup rpullup 0 0 * Set to vc to enable weak pullup
vpci rpci 0 0 * Set to vc to enable pci mode
vpcdp4 rpcdp4 0 rp4 * These control bits set the IO standard
vpcdp3 rpcdp3 0 rp3
vpcdp2 rpcdp2 0 rp2
vpcdp1 rpcdp1 0 rp1
vpcdp0 rpcdp0 0 rp0
vpcdn4 rpcdn4 0 rn4
vpcdn3 rpcdn3 0 rn3
vpcdn2 rpcdn2 0 rn2
vpcdn1 rpcdn1 0 rn1
vpcdn0 rpcdn0 0 rn0
vdin din 0 pulse(0 vc 0s 0.2ns 0.2ns 8.5ns 17.4ns)


  • Voltage source voeb controls the output enable of the buffer.
  • vopdrain controls the open drain mode for the I/O.
  • vrambh controls the bus hold circuitry in the I/O.
  • vrpullup controls the weak pullup.
  • vpci controls the PCI clamp.
  • The next ten voltage sources control the I/O standard of the buffer and are configured through a later library call.
  • vdin is connected to the data input of the I/O buffer.
  • The edge rate of the input stimulus is automatically set to the correct value by the Intel® Quartus® Prime software.

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