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1. Answers to Top FAQs
2. Signal Integrity Analysis with Third-Party Tools
3. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
4. Siemens EDA PCB Design Tools Support
5. Cadence Board Design Tools Support
6. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides
2.4.1. IBIS Model Access and Customization Flows
2.4.2. Elements of an IBIS Model
2.4.3. Customizing IBIS Models
2.4.4. Design Simulation Using the Siemens EDA HyperLynx* Software
2.4.5. Configuring LineSim to Use Intel IBIS Models
2.4.6. Integrating Intel IBIS Models into LineSim Simulations
2.4.7. Running and Interpreting LineSim Simulations
2.4.3.1. Customizing Downloaded IBIS Models for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices
2.4.3.2. Generate Custom IBIS Models with the EDA Netlist Writer GUI for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices
2.4.3.3. Customizing IBIS Model Files for Intel Agilex® 7 Devices
2.5.1. Supported Devices and Signaling
2.5.2. Accessing HSPICE Simulation Kits
2.5.3. The Double Counting Problem in HSPICE Simulations
2.5.4. HSPICE Writer Tool Flow
2.5.5. Running an HSPICE Simulation
2.5.6. Interpreting the Results of an Output Simulation
2.5.7. Interpreting the Results of an Input Simulation
2.5.8. Viewing and Interpreting Tabular Simulation Results
2.5.9. Viewing Graphical Simulation Results
2.5.10. Making Design Adjustments Based on HSPICE Simulations
2.5.11. Sample Input for I/O HSPICE Simulation Deck
2.5.12. Sample Output for I/O HSPICE Simulation Deck
2.5.13. Advanced Topics
2.5.4.1. Applying I/O Assignments
2.5.4.2. Enabling HSPICE Writer
2.5.4.3. Enabling HSPICE Writer Using Assignments
2.5.4.4. Naming Conventions for HSPICE Files
2.5.4.5. Invoking HSPICE Writer
2.5.4.6. Invoking HSPICE Writer from the Command Line
2.5.4.7. Customizing Automatically Generated HSPICE Decks
2.5.12.1. Header Comment
2.5.12.2. Simulation Conditions
2.5.12.3. Simulation Options
2.5.12.4. Constant Definition
2.5.12.5. I/O Buffer Netlist
2.5.12.6. Drive Strength
2.5.12.7. Slew Rate and Delay Chain
2.5.12.8. I/O Buffer Instantiation
2.5.12.9. Board and Trace Termination
2.5.12.10. Double-Counting Compensation Circuitry
2.5.12.11. Simulation Analysis
3.1. Reviewing Intel® Quartus® Prime Software Settings
3.2. Reviewing Device Pin-Out Information in the Fitter Report
3.3. Reviewing Compilation Error and Warning Messages
3.4. Using Additional Intel® Quartus® Prime Software Features
3.5. Using Additional Intel® Quartus® Prime Software Tools
3.6. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software Revision History
5.1. Cadence PCB Design Tools Support
5.2. Product Comparison
5.3. FPGA-to-PCB Design Flow
5.4. Setting Up the Intel® Quartus® Prime Software
5.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software
5.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software
5.7. Cadence Board Design Tools Support Revision History
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3.2. Reviewing Device Pin-Out Information in the Fitter Report
After you compile your design, you can use the reports in the Resource section of the Fitter report to check your device pin-out in detail.
The Input Pins, Output Pins, and Bidirectional Pins reports identify all the user I/O pins in your design and the features enabled for each I/O pin. For example, you can find use of weak internal pull-ups, PCI clamp diodes, and on-chip termination (OCT) pin assignments in these sections of the Fitter report. You can check the pin assignments reported in the Input Pins, Output Pins, and Bidirectional Pins reports against your PCB schematic to determine whether your PCB requires external components.
These reports also identify whether you made pin assignments or if the Fitter automatically placed the pins. If the Fitter changed your pin assignments, you should make these changes user assignments because the location of pin assignments made by the Fitter may change with subsequent compilations.
Figure 19. Resource Section ReportOpen the Compilation Report tab with Ctrl+R,. In the Plan Stage folder under Fitter open the Input Pins report. The following figure shows the pins the Fitter chose for the OCT external calibration resistor connections (RUP/RDN) and the name of the associated termination block in the Input Pins report. You should make these types of assignments user assignments.
The I/O Bank Usage report provides a high-level overview of the VCCIO and VREF requirements for your design, based on your I/O assignments. Verify that the requirements in this report match the settings in your PCB schematic. All unused I/O banks, and all banks with I/O pins with undefined I/O standards, default the VCCIO voltage to the voltage defined in the Voltage page of the Device and Pin Options dialog box.
The All Package Pins report lists all the pins on your device, including unused pins, dedicated pins and power/ground pins. You can use this report to verify pin characteristics, such as the location, name, usage, direction, I/O standard and voltage for each pin with the pin information in your PCB schematic. In particular, you should verify the recommended voltage levels at which you connect unused dedicated inputs and I/O and power pins, especially if you selected a migration device. Use the All Package Pins report to verify that you connected all the device voltage rails to the voltages reported.
Errors commonly reported include connecting the incorrect voltage to the predriver supply (VCCPD) pin in a specific bank, or leaving dedicated clock input pins floating. Unused input pins that should be connected to ground are designated as GND+ in the Pin Name/Usage column in the All Package Pins report.
You can also use the All Package Pins report to check transceiver-specific pin connections and verify that they match the PCB schematic. Unused transceiver pins have the following requirements, based on the pin designation in the Fitter report:
- GXB_GND—Unused GXB receiver or dedicated reference clock pin. This pin must be connected to GXB_GND through a 10k Ohm resistor.
- GXB_NC—Unused GXB transmitter or dedicated clock output pin. This pin must be disconnected.
Some transceiver power supply rails have dual voltage capabilities, such as VCCA_L/R and VCCH_L/R, that depend on the settings you created for the ALTGX parameter editor. Because these user-defined settings overwrite the default settings, you should use the All Package Pins report to verify that these power pins on the device symbol in the PCB schematics are connected to the voltage required by the transceiver. An incorrect connection may cause the transceiver to function not as expected.
If your design includes a memory interface, the DQS Summary report provides an overview of each DQ pin group. You can use this report to quickly confirm that the correct DQ/DQS pins are grouped together.
Finally, the Fitter Device Options report summarizes some of the settings made in the Device and Pin Options dialog box. Verify that these settings match your PCB schematics.