18.104.22.168. Header Comment
This block has two main components: The first component summarizes the I/O configuration relevant information such as device, speed grade, and so on. The second component specifies the exact test condition that the Intel® Quartus® Prime software assumes for the given I/O standard.
Sample Header Comment Block
* Intel Quartus Prime HSPICE Writer I/O Simulation Deck* * This spice simulation deck was automatically generated by * Quartus for the following IO settings: * * Device: EP2S60F1020C3 * Speed Grade: C3 * Pin: AA4 (out96) * Bank: IO Bank 6 (Row I/O) * I/O Standard: LVTTL, 12mA * OCT: Off * * Intel Quartus Prime’s default I/O timing delays assume the following slow * corner simulation conditions. * * Specified Test Conditions For Intel Quartus Prime Tco * Temperature: 85C (Slowest Temperature Corner) * Transistor Model: TT (Typical Transistor Corner) * Vccn: 3.135V (Vccn_min = Nominal - 5%) * Vccpd: 2.97V (Vccpd_min = Nominal - 10%) * Load: No Load * Vtt: 1.5675V (Voltage reference is Vccn/2) * * Note: The I/O transistors are specified to operate at least as * fast as the TT transistor corner, actual production * devices can be as fast as the FF corner. Any simulations * for hold times should be conducted using the fast process * corner with the following simulation conditions. * Temperature: 0C (Fastest Commercial Temperature Corner **) * Transistor Model: FF (Fastest Transistor Corner) * Vccn: 1.98V (Vccn_hold = Nominal + 10%) * Vccpd: 3.63V (Vccpd_hold = Nominal + 10%) * Vtt: 0.95V (Vtt_hold = Vccn/2 - 40mV) * Vcc: 1.25V (Vcc_hold = Maximum Recommended) * Package Model: Short-circuit from pad to pin (no parasitics) * * Warnings:
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