2.3.2. Customize the Output Files
If you generate IBIS files with the EDA Netlist Writer or IBIS Writer script, the IBIS Writer automatically customizes the files with the RLC values for the current target device. For details, refer to Simulation with IBIS Models.
HSPICE decks require modification to include a detailed description of your board. With Enable Advanced I/O Timing turned on and a board trace model defined in the Intel® Quartus® Prime software, generated HSPICE decks automatically include that model’s parameters. However, Intel recommends that you replace that model with a more detailed model that describes your board design more accurately. A default simulation included in the generated HSPICE decks measures delay between the FPGA and the far-end device.
You can make additions or adjustments to the default simulation in the generated files to change the parameters of the default simulation or to perform additional measurements. For details, refer to Simulation with HSPICE Models
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