1. Answers to Top FAQs 2. Signal Integrity Analysis with Third-Party Tools 3. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software 4. Siemens EDA PCB Design Tools Support 5. Cadence Board Design Tools Support 6. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
2.4.1. IBIS Model Access and Customization Flows 2.4.2. Elements of an IBIS Model 2.4.3. Customizing IBIS Models 2.4.4. Design Simulation Using the Siemens EDA HyperLynx* Software 2.4.5. Configuring LineSim to Use Intel IBIS Models 2.4.6. Integrating Intel IBIS Models into LineSim Simulations 2.4.7. Running and Interpreting LineSim Simulations
126.96.36.199. Customizing Downloaded IBIS Models for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices 188.8.131.52. Generate Custom IBIS Models with the EDA Netlist Writer GUI for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices 184.108.40.206. Customizing IBIS Model Files for Intel Agilex® 7 Devices
2.5.1. Supported Devices and Signaling 2.5.2. Accessing HSPICE Simulation Kits 2.5.3. The Double Counting Problem in HSPICE Simulations 2.5.4. HSPICE Writer Tool Flow 2.5.5. Running an HSPICE Simulation 2.5.6. Interpreting the Results of an Output Simulation 2.5.7. Interpreting the Results of an Input Simulation 2.5.8. Viewing and Interpreting Tabular Simulation Results 2.5.9. Viewing Graphical Simulation Results 2.5.10. Making Design Adjustments Based on HSPICE Simulations 2.5.11. Sample Input for I/O HSPICE Simulation Deck 2.5.12. Sample Output for I/O HSPICE Simulation Deck 2.5.13. Advanced Topics
220.127.116.11. Applying I/O Assignments 18.104.22.168. Enabling HSPICE Writer 22.214.171.124. Enabling HSPICE Writer Using Assignments 126.96.36.199. Naming Conventions for HSPICE Files 188.8.131.52. Invoking HSPICE Writer 184.108.40.206. Invoking HSPICE Writer from the Command Line 220.127.116.11. Customizing Automatically Generated HSPICE Decks
18.104.22.168. Header Comment 22.214.171.124. Simulation Conditions 126.96.36.199. Simulation Options 188.8.131.52. Constant Definition 184.108.40.206. I/O Buffer Netlist 220.127.116.11. Drive Strength 18.104.22.168. Slew Rate and Delay Chain 22.214.171.124. I/O Buffer Instantiation 126.96.36.199. Board and Trace Termination 188.8.131.52. Double-Counting Compensation Circuitry 184.108.40.206. Simulation Analysis
3.1. Reviewing Intel® Quartus® Prime Software Settings 3.2. Reviewing Device Pin-Out Information in the Fitter Report 3.3. Reviewing Compilation Error and Warning Messages 3.4. Using Additional Intel® Quartus® Prime Software Features 3.5. Using Additional Intel® Quartus® Prime Software Tools 3.6. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software Revision History
5.1. Cadence PCB Design Tools Support 5.2. Product Comparison 5.3. FPGA-to-PCB Design Flow 5.4. Setting Up the Intel® Quartus® Prime Software 5.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software 5.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software 5.7. Cadence Board Design Tools Support Revision History
220.127.116.11. Defining the Double Counting Problem
The double counting problem is inherent to the difference between the method to analyze output timing in the Intel® Quartus® Prime software versus the method HSPICE models use. The timing analyzer tools in the Intel® Quartus® Prime software measure delay timing for an output signal from the core logic of the FPGA design through the output buffer, ending at the FPGA pin with a default capacitive load or a specified value for the I/O standard you selected. This measurement is the tCO timing variable.
Figure 11. Double Counting Problem
HSPICE models for board simulation measure tPD (propagation delay) from an arbitrary reference point in the output buffer, through the device pin, out along the board routing, and ending at the signal destination.If you add these two delays, the delay between the output buffer and the device pin appears twice in the calculation. A model or simulation that does not account for this double count creates overly pessimistic simulation results, because the double-counted delay can limit I/O performance artificially.
One approach to fix the problem is subtracting the overlap between tCO and tPD to account for the double count. However, this adjustment is not accurate, because each measurement considers a different load.
Note: Input signals do not exhibit this problem, because the HSPICE models for inputs stop at the FPGA pin instead of at the input buffer. In this case, adding the delays together produces an accurate measurement of delay timing.