126.96.36.199. The Solution to Double Counting
With tTESTLOAD known, the total delay is calculated for the output signal from the FPGA logic to the signal destination on the board, accounting for the double count.
tdelay = tCO+(tPD-tTESTLOAD)
The preconfigured simulation files generated by the HSPICE Writer in the Intel® Quartus® Prime software are designed to account for the double-counting problem based on this calculation automatically.
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