220.127.116.11. Double-Counting Compensation Circuitry
As the amount of double-counting is constant for a given I/O standard on a given pin, consider separating the double-counting circuitry from the simulation file. In doing so, you can perform any number of I/O simulations while referencing the delay only once.
(Part of )Double-Counting Compensation Circuitry Block
* Double Counting Compensation Circuitry * * The following circuit is designed to calculate the amount of * double counting between Intel Quartus Prime and the HSPICE models. If * you have not changed the default simulation temperature or * transistor corner this spice deck automatically compensates the double counting. * In the event you wish to * simulate an IO at a different temperature or transistor corner * you need to remove this section of code and manually * account for double counting. A description of Intel’s * recommended procedure for this process can be found in the * Intel Quartus Prime HSPICE Writer AppNote. * Supply Voltages Settings .param vcn_tl=3.135 .param vpd_tl=2.97 * Test Load Constant Definition vopdrain_tl opdrain_tl 0 0 vrambh_tl rambh_tl 0 0 vrpullup_tl rpullup_tl 0 0 * Instantiate Power Supplies vvccn_tl vccn_tl 0 vcn_tl vvssn_tl vssn_tl 0 0 vvccpd_tl vccpd_tl 0 vpd_tl * Instantiate I/O Buffer xhio_testload din oeb opdrain_tl die_tl rambh_tl + rpcdn4 rpcdn3 rpcdn2 rpcdn1 rpcdn0 + rpcdp4 rpcdp3 rpcdp2 rpcdp1 rpcdp0 + rpullup_tl vccn_tl vccpd_tl vcpad0_tl hio_buf * Internal Loading on Pad xlvds_input_testload die_tl vss vccn_tl lvds_input_load xlvds_oct_testload die_tl vss vccpd_tl vccn_tl vcpad0_tl vccn_tl lvds_oct_load * I/O Buffer Package Model * - Single-ended I/O standard on a Row I/O .lib ‘lib/package.lib’ hio xpkg die pin hio_pkg * Default Intel Test Load * - 3.3V LVTTL default test condition is an open load
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