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1. Answers to Top FAQs
2. Signal Integrity Analysis with Third-Party Tools
3. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
4. Siemens EDA PCB Design Tools Support
5. Cadence Board Design Tools Support
6. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides
2.4.1. IBIS Model Access and Customization Flows
2.4.2. Elements of an IBIS Model
2.4.3. Customizing IBIS Models
2.4.4. Design Simulation Using the Siemens EDA HyperLynx* Software
2.4.5. Configuring LineSim to Use Intel IBIS Models
2.4.6. Integrating Intel IBIS Models into LineSim Simulations
2.4.7. Running and Interpreting LineSim Simulations
2.4.3.1. Customizing Downloaded IBIS Models for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices
2.4.3.2. Generate Custom IBIS Models with the EDA Netlist Writer GUI for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices
2.4.3.3. Customizing IBIS Model Files for Intel Agilex® 7 Devices
2.5.1. Supported Devices and Signaling
2.5.2. Accessing HSPICE Simulation Kits
2.5.3. The Double Counting Problem in HSPICE Simulations
2.5.4. HSPICE Writer Tool Flow
2.5.5. Running an HSPICE Simulation
2.5.6. Interpreting the Results of an Output Simulation
2.5.7. Interpreting the Results of an Input Simulation
2.5.8. Viewing and Interpreting Tabular Simulation Results
2.5.9. Viewing Graphical Simulation Results
2.5.10. Making Design Adjustments Based on HSPICE Simulations
2.5.11. Sample Input for I/O HSPICE Simulation Deck
2.5.12. Sample Output for I/O HSPICE Simulation Deck
2.5.13. Advanced Topics
2.5.4.1. Applying I/O Assignments
2.5.4.2. Enabling HSPICE Writer
2.5.4.3. Enabling HSPICE Writer Using Assignments
2.5.4.4. Naming Conventions for HSPICE Files
2.5.4.5. Invoking HSPICE Writer
2.5.4.6. Invoking HSPICE Writer from the Command Line
2.5.4.7. Customizing Automatically Generated HSPICE Decks
2.5.12.1. Header Comment
2.5.12.2. Simulation Conditions
2.5.12.3. Simulation Options
2.5.12.4. Constant Definition
2.5.12.5. I/O Buffer Netlist
2.5.12.6. Drive Strength
2.5.12.7. Slew Rate and Delay Chain
2.5.12.8. I/O Buffer Instantiation
2.5.12.9. Board and Trace Termination
2.5.12.10. Double-Counting Compensation Circuitry
2.5.12.11. Simulation Analysis
3.1. Reviewing Intel® Quartus® Prime Software Settings
3.2. Reviewing Device Pin-Out Information in the Fitter Report
3.3. Reviewing Compilation Error and Warning Messages
3.4. Using Additional Intel® Quartus® Prime Software Features
3.5. Using Additional Intel® Quartus® Prime Software Tools
3.6. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software Revision History
5.1. Cadence PCB Design Tools Support
5.2. Product Comparison
5.3. FPGA-to-PCB Design Flow
5.4. Setting Up the Intel® Quartus® Prime Software
5.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software
5.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software
5.7. Cadence Board Design Tools Support Revision History
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5.6.4. Splitting a Part
After saving a new symbol in a project library, you can fracture the symbol into multiple parts called sections. Fracturing a part into separate sections is useful for FPGA designs. A single symbol for most FPGA packages might be too large for a single schematic page. Splitting the part into separate sections allows you to organize parts of the symbol by function, creating cleaner circuit schematics. For example, you can create one slot for an I/O symbol, a second slot for a JTAG symbol, and a third slot for a power/ground symbol.
Figure 24. Splitting a Symbol into Multiple Sections
Note: Although symbol generation in the Design Entry CIS software refers to symbol fractures as sections, other tools use different names to refer to symbol fractures.
To split a part into sections, select the part in its library in the Project Manager window of the Cadence Allegro Design Entry CIS software. On the Tools menu, click Split Part or right-click the part and choose Split Part. The Split Part Section Input Spreadsheet appears.
Figure 25. Split Part Section Input Spreadsheet
Each row in the spreadsheet represents a pin in the symbol. The Section column indicates the section of the symbol to which each pin is assigned. You can locate all pins in a new symbol in section 1. You can change the values in the Section column to assign pins to various sections of the symbol. You can also specify the side of a section on the location of the pin by changing the values in the Location column. When you are ready, click Split. A new symbol appears in the same library as the original with the name <original part name>_Split1.
View and edit each section individually. To view the new sections of the part, double-click the part. The Part Symbol Editor window appears and the first section of the part displays for editing. On the View menu, click Package to view thumbnails of all the part sections. To edit the section of the symbol, double-click the thumbnail.
For more information about splitting parts into sections and editing symbol sections in the Cadence Allegro Design Entry CIS software, refer to the Help in the software.