Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

Download PDF
ID 683768
Date 8/01/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Signal Integrity Analysis with Third-Party Tools 3. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software 4. Siemens EDA PCB Design Tools Support 5. Cadence Board Design Tools Support 6. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Signal Integrity Analysis with Third-Party Tools x
2.1. Signal Integrity Analysis with Third-Party Tools 2.2. I/O Model Selection: IBIS or HSPICE 2.3. FPGA to Board Signal Integrity Analysis Flow 2.4. Simulation with IBIS Models 2.5. Simulation with HSPICE Models 2.6. Signal Integrity Analysis with Third-Party Tools Document Revision History
2.1. Signal Integrity Analysis with Third-Party Tools x
2.1.1. What's New In This Version 2.1.2. Signal Integrity Simulations with HSPICE and IBIS Models
2.3. FPGA to Board Signal Integrity Analysis Flow x
2.3.1. Create I/O and Board Trace Model Assignments 2.3.2. Customize the Output Files 2.3.3. Set Up and Run Simulations in Third-Party Tools 2.3.4. Interpret Simulation Results
2.4. Simulation with IBIS Models x
2.4.1. IBIS Model Access and Customization Flows 2.4.2. Elements of an IBIS Model 2.4.3. Customizing IBIS Models 2.4.4. Design Simulation Using the Siemens EDA HyperLynx* Software 2.4.5. Configuring LineSim to Use Intel IBIS Models 2.4.6. Integrating Intel IBIS Models into LineSim Simulations 2.4.7. Running and Interpreting LineSim Simulations
2.4.3. Customizing IBIS Models x
2.4.3.1. Customizing Downloaded IBIS Models for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices 2.4.3.2. Generate Custom IBIS Models with the EDA Netlist Writer GUI for Intel® Stratix® 10 Devices, Intel® Arria® 10 Devices, and Intel® Cyclone® 10 GX Devices 2.4.3.3. Customizing IBIS Model Files for Intel Agilex® 7 Devices
2.5. Simulation with HSPICE Models x
2.5.1. Supported Devices and Signaling 2.5.2. Accessing HSPICE Simulation Kits 2.5.3. The Double Counting Problem in HSPICE Simulations 2.5.4. HSPICE Writer Tool Flow 2.5.5. Running an HSPICE Simulation 2.5.6. Interpreting the Results of an Output Simulation 2.5.7. Interpreting the Results of an Input Simulation 2.5.8. Viewing and Interpreting Tabular Simulation Results 2.5.9. Viewing Graphical Simulation Results 2.5.10. Making Design Adjustments Based on HSPICE Simulations 2.5.11. Sample Input for I/O HSPICE Simulation Deck 2.5.12. Sample Output for I/O HSPICE Simulation Deck 2.5.13. Advanced Topics
2.5.3. The Double Counting Problem in HSPICE Simulations x
2.5.3.1. Defining the Double Counting Problem 2.5.3.2. The Solution to Double Counting
2.5.4. HSPICE Writer Tool Flow x
2.5.4.1. Applying I/O Assignments 2.5.4.2. Enabling HSPICE Writer 2.5.4.3. Enabling HSPICE Writer Using Assignments 2.5.4.4. Naming Conventions for HSPICE Files 2.5.4.5. Invoking HSPICE Writer 2.5.4.6. Invoking HSPICE Writer from the Command Line 2.5.4.7. Customizing Automatically Generated HSPICE Decks
2.5.11. Sample Input for I/O HSPICE Simulation Deck x
2.5.11.1. Header Comment 2.5.11.2. Simulation Conditions 2.5.11.3. Simulation Options 2.5.11.4. Constant Definition 2.5.11.5. Buffer Netlist 2.5.11.6. Drive Strength 2.5.11.7. I/O Buffer Instantiation 2.5.11.8. Board Trace and Termination 2.5.11.9. Stimulus Model 2.5.11.10. Simulation Analysis
2.5.12. Sample Output for I/O HSPICE Simulation Deck x
2.5.12.1. Header Comment 2.5.12.2. Simulation Conditions 2.5.12.3. Simulation Options 2.5.12.4. Constant Definition 2.5.12.5. I/O Buffer Netlist 2.5.12.6. Drive Strength 2.5.12.7. Slew Rate and Delay Chain 2.5.12.8. I/O Buffer Instantiation 2.5.12.9. Board and Trace Termination 2.5.12.10. Double-Counting Compensation Circuitry 2.5.12.11. Simulation Analysis
2.5.13. Advanced Topics x
2.5.13.1. PVT Simulations 2.5.13.2. Hold Time Analysis 2.5.13.3. I/O Voltage Variations 2.5.13.4. Correlation Report
3. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software x
3.1. Reviewing Intel® Quartus® Prime Software Settings 3.2. Reviewing Device Pin-Out Information in the Fitter Report 3.3. Reviewing Compilation Error and Warning Messages 3.4. Using Additional Intel® Quartus® Prime Software Features 3.5. Using Additional Intel® Quartus® Prime Software Tools 3.6. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software Revision History
3.1. Reviewing Intel® Quartus® Prime Software Settings x
3.1.1. Device and Pins Options Dialog Box Settings
3.1.1. Device and Pins Options Dialog Box Settings x
3.1.1.1. Configuration Settings 3.1.1.2. Unused Pin Settings 3.1.1.3. Dual-Purpose Pins Settings 3.1.1.4. Voltage Settings 3.1.1.5. Error Detection CRC Settings
3.5. Using Additional Intel® Quartus® Prime Software Tools x
3.5.1. Pin Planner
4. Siemens EDA PCB Design Tools Support x
4.1. Integrating with DxDesigner 4.2. Siemens EDA PCB Design Tools Support Revision History
4.1. Integrating with DxDesigner x
4.1.1. DxDesigner Project Settings 4.1.2. Creating Schematic Symbols in DxDesigner
5. Cadence Board Design Tools Support x
5.1. Cadence PCB Design Tools Support 5.2. Product Comparison 5.3. FPGA-to-PCB Design Flow 5.4. Setting Up the Intel® Quartus® Prime Software 5.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software 5.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software 5.7. Cadence Board Design Tools Support Revision History
5.3. FPGA-to-PCB Design Flow x
5.3.1. Integrating Intel FPGA Designs
5.4. Setting Up the Intel® Quartus® Prime Software x
5.4.1. Generating a .pin File
5.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software x
5.5.1. Creating Symbols 5.5.2. Instantiating the Symbol in the Cadence Allegro Design Entry HDL Software
5.5.1. Creating Symbols x
5.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool
5.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool x
5.5.1.1.1. Cadence Allegro PCB Librarian Part Developer Tool in the Design Flow 5.5.1.1.2. Import and Export Wizard 5.5.1.1.3. Editing and Fracturing Symbol 5.5.1.1.4. Updating FPGA Symbols
5.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software x
5.6.1. Creating a Cadence Allegro Design Entry CIS Project 5.6.2. Generating a Part 5.6.3. Generating Schematic Symbol 5.6.4. Splitting a Part 5.6.5. Instantiating a Symbol in a Design Entry CIS Schematic 5.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software
5.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software x
5.6.6.1. Using the Intel-provided Libraries with your Cadence Allegro Design Entry CIS Project
1. Answers to Top FAQs
2. Signal Integrity Analysis with Third-Party Tools
3. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
4. Siemens EDA PCB Design Tools Support
5. Cadence Board Design Tools Support
6. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

2.5.10. Making Design Adjustments Based on HSPICE Simulations

Based on the results of your simulations, you can make adjustments to the I/O assignments or simulation parameters if required. For example, after you run a simulation and see overshoot or ringing in the simulated signal at the destination buffer, you can adjust the drive strength I/O assignment setting to a lower value. Regenerate the HSPICE deck, and run the simulation again to verify that the change fixed the problem.
Figure 17. Example of Overshoot in the AvanWaves Waveform Viewer

If there is a discontinuity or any other anomalies at the destination, adjust the board description in the Intel® Quartus® Prime Board Trace Model, or in the generated HSPICE model files to change the termination scheme or adjust termination component values. After making these changes, regenerate the HSPICE files if necessary, and rerun the simulation to verify whether your adjustments solved the problem.

Figure 18. Example of Signal Integrity Anomaly in the AvanWaves Waveform Viewer

For more information about board-level signal integrity and to learn about ways to improve it with simple changes to your FPGA design, visit the Intel Signal & Power Integrity Center

Related Information
Level Two Title