Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 8/01/2023

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2.5.10. Making Design Adjustments Based on HSPICE Simulations

Based on the results of your simulations, you can make adjustments to the I/O assignments or simulation parameters if required. For example, after you run a simulation and see overshoot or ringing in the simulated signal at the destination buffer, you can adjust the drive strength I/O assignment setting to a lower value. Regenerate the HSPICE deck, and run the simulation again to verify that the change fixed the problem.
Figure 17. Example of Overshoot in the AvanWaves Waveform Viewer

If there is a discontinuity or any other anomalies at the destination, adjust the board description in the Intel® Quartus® Prime Board Trace Model, or in the generated HSPICE model files to change the termination scheme or adjust termination component values. After making these changes, regenerate the HSPICE files if necessary, and rerun the simulation to verify whether your adjustments solved the problem.

Figure 18. Example of Signal Integrity Anomaly in the AvanWaves Waveform Viewer

For more information about board-level signal integrity and to learn about ways to improve it with simple changes to your FPGA design, visit the Intel Signal & Power Integrity Center