2.4.3. Customizing IBIS Models
There are different options for obtaining and customizing Intel FPGA IBIS models, depending on your target device family, as IBIS Model Access and Customization Flows describes. The following topics describe these different options for obtaining and customizing Intel FPGA IBIS models.
The IBIS file that the Intel® Quartus® Prime EDA Netlist Writer GUI generates contains models of both input and output termination, and is supported for IBIS model versions of 4.2 and later.
The Intel® Quartus® Prime IBIS dynamic OCT IBIS model names end in g50c_r50c. For example : sstl15i_ctnio_g50c_r50c.
When the buffer is assigned as an output, use the series termination r50c.
When the buffer is assigned as an input, use the parallel termination g50c.
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