Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 8/01/2023

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Document Table of Contents I/O Buffer Instantiation

The I/O buffer instantiation block of the output simulation spice deck instantiates the necessary power supplies and I/O model components that are necessary to simulate the given I/O.

 I/O Buffer Instantiation Block

* I/O Buffer Instantiation
* Supply Voltages Settings
.param vcn=3.135
.param vpd=2.97
.param vc=1.15
* Instantiate Power Supplies
vvcc vcc 0 vc * FPGA core voltage
vvss vss 0 0 * FPGA core ground
vvccn vccn 0 vcn * IO supply voltage
vvssn vssn 0 0 * IO ground
vvccpd vccpd 0 vpd * Pre-drive supply voltage
* Instantiate I/O Buffer
xhio_buf din oeb opdrain die rambh
+ rpcdn4 rpcdn3 rpcdn2 rpcdn1 rpcdn0
+ rpcdp4 rpcdp3 rpcdp2 rpcdp1 rpcdp0
+ rpullup vccn vccpd vcpad0 hio_buf
* Internal Loading on Pad
* - This pad has an LVDS input buffer connected to it, along
* with differential OCT circuitry. Both are disabled but
* introduce loading on the pad that is modeled below.
xlvds_input_load die vss vccn lvds_input_load
xlvds_oct_load die vss vccpd vccn vcpad0 vccn lvds_oct_load
* I/O Buffer Package Model
* - Single-ended I/O standard on a Row I/O
.lib ‘lib/package.lib’ hio
xpkg die pin hio_pkg