Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 11/04/2020
Public
Document Table of Contents

1.5.3.2. The Solution to Double Counting

To adjust the measurements to account for the double-counting, the delay between the arbitrary point in the output buffer selected by the HSPICE model and the FPGA pin must be subtracted from either tCO or tPD before adding the results together. The subtracted delay must also be based on a common load between the two measurements. This is done by repeating the HSPICE model measurement, but with the same load used by the Intel® Quartus® Prime software for the tCO measurement.
Figure 11. Common Test Loads Used for Output Timing

With tTESTLOAD known, the total delay is calculated for the output signal from the FPGA logic to the signal destination on the board, accounting for the double count.

tdelay = tCO+(tPD-tTESTLOAD)

The preconfigured simulation files generated by the HSPICE Writer in the Intel® Quartus® Prime software are designed to account for the double-counting problem based on this calculation automatically.

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