Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 11/04/2020
Document Table of Contents Simulation Analysis

The simulation analysis block is set up to measure double-counting corrected delays. This is accomplished by measuring the uncompensated delay of the I/O buffer when connected to the user load, and when subtracting the simulated amount of double-counting from the test load I/O buffer.

Simulation Analysis Block

* Simulation Analysis Setup

*Print out the voltage waveform at both the pin and far end load
.print tran v(pin) v(load)
.tran 0.020ns 17ns

* Measure the propagation delay to the load pin. This value 
* includes some double counting with 
               Quartus® Prime’s Tco
.measure TRAN tpd_uncomp_rise TRIG v(din) val=’vc*0.5’ rise=1+ TARG v(load) val=’vcn*0.5’ rise=1
.measure TRAN tpd_uncomp_fall TRIG v(din) val=’vc*0.5’ fall=1
    	+ TARG v(load) val=’vcn*0.5’ fall=1
* The test load buffer can calculate the amount of double counting
.measure TRAN t_dblcnt_rise TRIG v(din) val=’vc*0.5’ rise=1
+ TARG v(pin_tl) val=’vcn_tl*0.5’ rise=1
.measure TRAN t_dblcnt_fall TRIG v(din) val=’vc*0.5’ fall=1
+ TARG v(pin_tl) val=’vcn_tl*0.5’ fall=1

* Calculate the true propagation delay by subtraction
.measure TRAN tpd_rise PARAM=’tpd_uncomp_rise-t_dblcnt_rise’
.measure TRAN tpd_fall PARAM=’tpd_uncomp_fall-t_dblcnt_fall’

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