1.5.3. The Double Counting Problem in HSPICE Simulations
Simulating I/Os using accurate models is extremely helpful for finding and fixing FPGA I/O timing and board signal integrity issues before any boards are built. However, the usefulness of such simulations is directly related to the accuracy of the models used and whether the simulations are set up and performed correctly.
To ensure accuracy in models and simulations created for FPGA output signals you must consider the timing hand-off between tCO timing in the Intel® Quartus® Prime software and simulation-based board delay. If this hand-off is not handled correctly, the calculated delay could either count some of the delay twice or even miss counting some of the delay entirely.
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