1.5.10. Making Design Adjustments Based on HSPICE Simulations
If there is a discontinuity or any other anomalies at the destination, adjust the board description in the Intel® Quartus® Prime Board Trace Model, or in the generated HSPICE model files to change the termination scheme or adjust termination component values. After making these changes, regenerate the HSPICE files if necessary, and rerun the simulation to verify whether your adjustments solved the problem.
For more information about board-level signal integrity and to learn about ways to improve it with simple changes to your FPGA design, visit the Intel Signal & Power Integrity Center
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