Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 11/04/2020
Public
Document Table of Contents

1.5.6. Interpreting the Results of an Output Simulation

By default, the automatically generated output simulation spice decks are set up to measure three delays for both rising and falling transitions. Two of the measurements, tpd_rise and tpd_fall, measure the double-counting corrected delay from the FPGA pin to the load pin. To determine the complete clock-edge to load-pin delay, add these numbers to the Intel® Quartus® Prime software reported default loading tCO delay.

The remaining four measurements, tpd_uncomp_rise, tpd_uncomp_fall, t_dblcnt_rise, and t_dblcnt_fall, are required for the double-counting compensation process and are not required for further timing usage.

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