Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools
ID
683768
Date
11/04/2020
Public
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1. Signal Integrity Analysis with Third-Party Tools
2. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
3. Mentor Graphics* PCB Design Tools Support
4. Cadence Board Design Tools Support
5. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides
1.4.1. Elements of an IBIS Model
1.4.2. Creating Accurate IBIS Models
1.4.3. Design Simulation Using the Mentor Graphics* HyperLynx* Software
1.4.4. Configuring LineSim to Use Intel IBIS Models
1.4.5. Integrating Intel IBIS Models into LineSim Simulations
1.4.6. Running and Interpreting LineSim Simulations
1.5.1. Supported Devices and Signaling
1.5.2. Accessing HSPICE Simulation Kits
1.5.3. The Double Counting Problem in HSPICE Simulations
1.5.4. HSPICE Writer Tool Flow
1.5.5. Running an HSPICE Simulation
1.5.6. Interpreting the Results of an Output Simulation
1.5.7. Interpreting the Results of an Input Simulation
1.5.8. Viewing and Interpreting Tabular Simulation Results
1.5.9. Viewing Graphical Simulation Results
1.5.10. Making Design Adjustments Based on HSPICE Simulations
1.5.11. Sample Input for I/O HSPICE Simulation Deck
1.5.12. Sample Output for I/O HSPICE Simulation Deck
1.5.13. Advanced Topics
1.5.4.1. Applying I/O Assignments
1.5.4.2. Enabling HSPICE Writer
1.5.4.3. Enabling HSPICE Writer Using Assignments
1.5.4.4. Naming Conventions for HSPICE Files
1.5.4.5. Invoking HSPICE Writer
1.5.4.6. Invoking HSPICE Writer from the Command Line
1.5.4.7. Customizing Automatically Generated HSPICE Decks
1.5.12.1. Header Comment
1.5.12.2. Simulation Conditions
1.5.12.3. Simulation Options
1.5.12.4. Constant Definition
1.5.12.5. I/O Buffer Netlist
1.5.12.6. Drive Strength
1.5.12.7. Slew Rate and Delay Chain
1.5.12.8. I/O Buffer Instantiation
1.5.12.9. Board and Trace Termination
1.5.12.10. Double-Counting Compensation Circuitry
1.5.12.11. Simulation Analysis
2.1. Reviewing Intel® Quartus® Prime Software Settings
2.2. Reviewing Device Pin-Out Information in the Fitter Report
2.3. Reviewing Compilation Error and Warning Messages
2.4. Using Additional Intel® Quartus® Prime Software Features
2.5. Using Additional Intel® Quartus® Prime Software Tools
2.6. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software Revision History
4.1. Cadence PCB Design Tools Support
4.2. Product Comparison
4.3. FPGA-to-PCB Design Flow
4.4. Setting Up the Intel® Quartus® Prime Software
4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software
4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software
4.7. Cadence Board Design Tools Support Revision History
2.1.1.4. Voltage Settings
The Voltage page specifies the default VCCIO I/O bank voltage and the default I/O bank voltage for the pins on the target device. VCCIO I/O bank voltage settings made in the Voltage page are overridden by I/O standard assignments made on I/O pins in their respective banks.
Ensure that the settings in the Voltage page match the settings in your PCB schematic, especially if the target device includes transceivers.
The Voltage page settings requirements differ depending on the settings of the transceiver instances in the design. Refer to the Fitter report for the required settings, and verify that the voltage settings are correctly set up for your PCB schematic.
After verifying your settings in the Device and Settings dialog boxes, you can verify your device pin-out with the Fitter report.
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