Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 11/04/2020
Public
Document Table of Contents

4.5.1.1.3. Editing and Fracturing Symbol

After creating your new symbol in the Cadence Allegro PCB Librarian Part Developer tool, you can edit the symbol graphics, fracture the symbol into multiple slots, and add or change package or symbol properties.

The Part Developer Symbol Editor contains many graphical tools to edit the graphics of a particular symbol. To edit the symbol graphics, select the symbol in the cell hierarchy. The Symbol Pins tab appears. You can edit the preview graphic of the symbol in the Symbol Pins tab.

Fracturing a Cadence Allegro PCB Librarian Part Developer package into separate symbol slots is useful for FPGA designs. A single symbol for most FPGA packages might be too large for a single schematic page. Splitting the part into separate slots allows you to organize parts of the symbol by function, creating cleaner circuit schematics. For example, you can create one slot for an I/O symbol, a second slot for a JTAG symbol, and a third slot for a power/ground symbol.

Figure 20. Splitting a Symbol into Multiple Slots


To fracture a part into separate slots, or to modify the slot locations of pins on parts fractured in the Cadence Allegro PCB Librarian Part Developer tool, follow these steps:

  1. Start the Cadence Allegro Design Project Manager.
  2. On the Flows menu, click Library Management.
  3. Click Part Developer.
  4. Click the name of the package you want to change in the cell hierarchy.
  5. Click Functions/Slots. If you are not creating new slots but want to change the slot location of some pins, proceed to Step 6. If you are creating new slots, click Add. A dialog box appears, allowing you to add extra symbol slots. Set the number of extra slots you want to add to the existing symbol, not the total number of desired slots for the part. Click OK.
  6. Click Distribute Pins. Specify the slot location for each pin. Use the checkboxes in each column to move pins from one slot to another. Click OK.
  7. After distributing the pins, click the Package Pin tab and click Generate Symbol(s).
  8. Select whether to create a new symbol or modify an existing symbol in each slot. Click OK.

    The newly generated or modified slot symbols appear as separate symbols in the cell hierarchy. Each of these symbols can be edited individually.

    CAUTION:
    The Cadence Allegro PCB Librarian Part Developer tool allows you to remap pin assignments in the Package Pin tab of the main Cadence Allegro PCB Librarian Part Developer window. If signals remap to different pins in the Cadence Allegro PCB Librarian Part Developer tool, the changes reflect only in regenerated symbols for use in your schematics. You cannot transfer pin assignment changes to the Intel® Quartus® Prime software from the Cadence Allegro PCB Librarian Part Developer tool, which creates a potential mismatch of the schematic symbols and assignments in the FPGA design. If pin assignment changes are necessary, make the changes in the Intel® Quartus® Prime Pin Planner instead of the Cadence Allegro PCB Librarian Part Developer tool, and update the symbol as described in the following sections.

    For more information about creating, editing, and organizing component symbols with the Cadence Allegro PCB Librarian Part Developer tool, refer to the Part Developer Help.

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