Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 11/04/2020
Public
Document Table of Contents

1.5.7. Interpreting the Results of an Input Simulation

By default, the automatically generated input simulation SPICE decks are set up to measure delays from the source’s driver pin to the FPGA’s input pin for both rising and falling transitions.

The propagation delay is reported by HSPICE measure statements as tpd_rise and tpd_fall. To determine the complete source driver pin-to-FPGA register delay, add these numbers to the Intel® Quartus® Prime software reported TH and TSU input timing numbers.

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