The double counting problem is inherent to the difference between the method to analyze output timing in the Intel® Quartus® Prime software versus the method HSPICE models use. The timing analyzer tools in the Intel® Quartus® Prime software measure delay timing for an output signal from the core logic of the FPGA design through the output buffer, ending at the FPGA pin with a default capacitive load or a specified value for the I/O standard you selected. This measurement is the tCO timing variable.
HSPICE models for board simulation measure tPD (propagation delay) from an arbitrary reference point in the output buffer, through the device pin, out along the board routing, and ending at the signal destination.
If you add these two delays, the delay between the output buffer and the device pin appears twice in the calculation. A model or simulation that does not account for this double count creates overly pessimistic simulation results, because the double-counted delay can limit I/O performance artificially.
One approach to fix the problem is subtracting the overlap between tCO
to account for the double count. However, this adjustment is not accurate, because each measurement considers a different load.
Note: Input signals do not exhibit this problem, because the HSPICE models for inputs stop at the FPGA pin instead of at the input buffer. In this case, adding the delays together produces an accurate measurement of delay timing.