Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 11/04/2020
Public
Document Table of Contents

1.5.8. Viewing and Interpreting Tabular Simulation Results

The .lis file stores the collected simulation data in tabular form. The default simulation configured by the HSPICE Writer produces delay measurements for rising and falling transitions on both input and output simulations.

These measurements are found in the .lis file and named tpd_rise and tpd_fall. For output simulations, these values are already adjusted for the double count. To determine the complete delay from the FPGA logic to the load pin, add either of these measurements to the Intel® Quartus® Prime tCO delay. For input simulations, add either of these measurements to the Intel® Quartus® Prime tSU and tH delay values to calculate the complete delay from the far end stimulus to the FPGA logic. Other values found in the .lis file, such as tpd_uncomp_rise, tpd_uncomp_fall, t_dblcnt_rise, and t_dblcnt_fall, are parts of the double count compensation calculation. These values are not necessary for further analysis.

Did you find the information on this page useful?

Characters remaining:

Feedback Message