Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

ID 683768
Date 11/04/2020
Document Table of Contents Generate Custom IBIS Models with the IBIS Writer

If you have started your FPGA design and have created custom I/O assignments, you can use the Intel® Quartus® Prime IBIS Writer to create custom IBIS models to accurately reflect your assignments.

Examples of custom assignments include drive strength settings or the enabling of clamping diodes for ESD protection. IBIS models created with the IBIS Writer take I/O assignment settings into account.

If the Enable Advanced I/O Timing option is turned off, the generated .ibs files are based on the load value setting for each I/O standard on the Capacitive Loading page of the Device and Pin Options dialog box in the Device dialog box. With the Enable Advanced I/O Timing option turned on, IBIS models use an effective capacitive load based on settings found in the board trace model on the Board Trace Model page in the Device and Pin Options dialog box or the Board Trace Model view in the Pin Planner. The effective capacitive load is based on the sum of the Near capacitance, Transmission line distributed capacitance, and the Far capacitance settings in the board trace model. Resistance values and transmission line inductance values are ignored.

Note: If you made any changes from the default load settings, the delay in the generated IBIS model cannot safely be added to the Intel® Quartus® Prime tCO measurement to account for the double counting problem. This is because the load values between the two delay measurements do not match. When this happens, the Intel® Quartus® Prime software displays warning messages when the EDA Netlist Writer runs to remind you about the load value mismatch.

Did you find the information on this page useful?

Characters remaining:

Feedback Message