Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents

1.1. Power Reduction

Power reduction on SoC FPGAs can be broken up into methods focused on the Hard Processor System (HPS) and FPGA portions of the device.

Refer to the appendix for power measurement techniques and instructions on how to set-up your Cyclone V SoC development kit.