Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents

1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations

The two important time periods to consider when reapplying power to the FPGA portion of the SoC device are the power on time (system/power management specific) and the FPGA configuration time.

Note: “Power on time” refers to how long it takes for the FPGA power rails to reach nominal voltage levels.

Of these two, configuration time dominates and is dependent on the mode of configuration selected. From the programming examples shipped as part of the SoCEDS software ($SOCEDS_DEST_ROOT/examples/software/Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU.tar.gz), the following steps are used to program the FPGA:

  1. The “power on” bit (in the FPGA manager’s status register) is checked to see if the FPGA is on.
    • If off, configuration fails.
    • If on, the HPS takes control of the configuration block.
  2. The MSEL (configuration mode bits) are read.
    Note: Only the modes listed in the FPGA Manager chapter in the Cyclone V reference manual are supported.
  3. If the MSEL are set to a supported mode, a DMA is configured to transfer data from a buffer into the FPGA configuration block.
    • Data is written (4 bytes at a time) into the configuration block.
  4. On success, the FPGA completes configuration and enters user mode.

Given that the binary files used to configure the FPGA (.rbf: raw binary files) are in the range of 7 MB, the following table estimates configuration times:

Table 3.  FPGA Configuration Times based on Configuration Type
Configuration Type Approximate Time (seconds)
HPS Configuration 0.15-0.2
Active Serial (via external EPCQ) 1.0

These configuration times assume .sof/.rbf is resident in SDRAM.

For more information about the configuration process, refer to the FPGA Manager chapter in the Cyclone V Hard Processor System Technical Reference Manual, Volume 3.