Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents

1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration

There are two stages to restoring FPGA functionality:

  • FPGA power up
  • FPGA configuration

For typical designs, writing a 1 to the GPIO that is connected to CONTROL0 (or CONTROL1) triggers power up. However, with the LTPowerPlay probe connected, this operation cannot function due to the removal of the I2C resistors. With the probe connected, power must be applied through the probe by individually powering up each rail. FPGA configuration/re-configuration is necessary after power-up. The FPGA image can be pulled from many options such as the EPCQ device or loaded from the HPS side.

Refer to the "Requirements" section of this app note for information regarding the removal of the I2C resistors.