Cyclone V SoC Power Optimization

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ID 683713
Date 2/09/2015
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V SoC Power Optimization
1. Cyclone V SoC Power Optimization x
1.1. Power Reduction 1.2. HPS Power Reduction Methods 1.3. FPGA Power Reduction Methods 1.4. Power Optimization Summary 1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit
1.2. HPS Power Reduction Methods x
1.2.1. MPU 1.2.2. Peripherals 1.2.3. HPS Power Reduction Summary
1.2.1. MPU x
1.2.1.1. HPS Method 1: Fit Code in Cache 1.2.1.2. HPS Method 2: Processor Standby Modes and Dynamic Clock Gating 1.2.1.3. HPS Method 3: CPU1 in WFI/WFE or Standby Loop 1.2.1.4. HPS Method 4: Lowering CPU Frequency
1.2.2. Peripherals x
1.2.2.1. HPS Method 5: Energy Efficient Ethernet 1.2.2.2. HPS Method 6: USB Power Management 1.2.2.3. HPS Method 7: Unused Peripherals in Reset
1.3. FPGA Power Reduction Methods x
1.3.1. FPGA Power Consumption 1.3.2. FPGA Portion Power Down 1.3.3. FPGA Power Off Step 1: Board Design (Power Rail) Choices 1.3.4. FPGA Power Off Step 2: Quiet FPGA 1.3.5. FPGA Power Off Step 3: Power Off the FPGA 1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration 1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit x
1.5.1. Power Monitoring and Measurement 1.5.2. Cyclone V SoC Development Kit Power Management ICs 1.5.3. Cyclone V SoC Development Kit Power Monitor Application 1.5.4. LTC LTpower Play Tool 1.5.5. Using the LTC2978A Linux Driver 1.5.6. Power Measurement Results on Cyclone V SoC Development Kit 1.5.7. Document Revision History
1.5.3. Cyclone V SoC Development Kit Power Monitor Application x
1.5.3.1. Starting the Application 1.5.3.2. Windows Instructions 1.5.3.3. Linux Instructions
1.5.4. LTC LTpower Play Tool x
1.5.4.1. Requirements 1.5.4.2. LTC Video Tutorial
1.5.5. Using the LTC2978A Linux Driver x
1.5.5.1. Compiling the Driver 1.5.5.2. Using the Driver
1. Cyclone V SoC Power Optimization

1.2.3. HPS Power Reduction Summary

There are several methods for reducing HPS power consumption.

  1. Fit code in cache
    • Ensure that the loop you're running (code and data being accessed) doesn't consume more than the 512Kb of L2 cache.
  2. Processor standby modes and clock gating
    • Follow the instructions preceding the WFI/WFE call to take advantage of dynamic clock gating in the MPU
    • Issue WFI or WFE instructions to enter standby mode
      • Entering this mode engages any dynamic clock gating logic you’ve enabled
  3. Put CPU1 in WFI/WFE or “standby loop” when CPU1 is not be used in your system.
  4. Reduce the overall CPU clock frequency
  5. Utilize low power modes in Ethernet
  6. Utilize low power modes in the USB controller
  7. Hold unused peripherals in reset

The table below gives an order of magnitude estimate of the potential power savings that can be gained using each of these methods:

Table 2.  Order of Magnitude Power Savings for HPS Power Reduction Methods
HPS Power Saving Method Approximate Power Reduction
Code Loop in L2 Cache 400 mW
CPU Frequency Reduction ~0.475 mW/MHz
WFI/WFE or Standby Loop 200 mW
WFI/WFE vs CPU1 held in reset 90 mW1
Ethernet EEE/Idle 20-30 mW
USB Idle 10-15 mW
Note: These numbers are approximate and are provided to give visibility to relative power reduction gains for the listed methods. They are provided to help prioritize power saving efforts for the biggest payoff. They are not guaranteed and will vary from system to system or SoC to SoC. All numbers with the exception of the "Frequency Reduction" are based on an 800 MHz CPU clock.
Related Information
1 It is best to put an unused core in a WFE/WFI loop to take advantage of the power reduction.
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