1.3.1. FPGA Power Consumption 1.3.2. FPGA Portion Power Down 1.3.3. FPGA Power Off Step 1: Board Design (Power Rail) Choices 1.3.4. FPGA Power Off Step 2: Quiet FPGA 1.3.5. FPGA Power Off Step 3: Power Off the FPGA 1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration 1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
1.5.1. Power Monitoring and Measurement 1.5.2. Cyclone V SoC Development Kit Power Management ICs 1.5.3. Cyclone V SoC Development Kit Power Monitor Application 1.5.4. LTC LTpower Play Tool 1.5.5. Using the LTC2978A Linux Driver 1.5.6. Power Measurement Results on Cyclone V SoC Development Kit 1.5.7. Document Revision History
1.3.5. FPGA Power Off Step 3: Power Off the FPGA
Because there are no sequencing requirements for powering off the FPGA portion of the SoC device, issue the power off command that is needed to trigger the power management for your system to power off the FPGA portion.
For instance, it’s common to make use of the CONTROL0 or CONTROL1 pin on the LTC2978 device to control power on/off in a system. Routing either or both of these pins to a GPIO on the HPS side of the SoC device and then writing a 0 or 1 to the pin can power cycle the FPGA portion.
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