Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents

1.3.5. FPGA Power Off Step 3: Power Off the FPGA

Because there are no sequencing requirements for powering off the FPGA portion of the SoC device, issue the power off command that is needed to trigger the power management for your system to power off the FPGA portion.

For instance, it’s common to make use of the CONTROL0 or CONTROL1 pin on the LTC2978 device to control power on/off in a system. Routing either or both of these pins to a GPIO on the HPS side of the SoC device and then writing a 0 or 1 to the pin can power cycle the FPGA portion.