Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents

1.3. FPGA Power Reduction Methods

The Cyclone V FPGA power consumption reduction techniques are well documented on Altera’s website and in numerous academic and industry documents. Any FPGA power reduction method that applies to the Cyclone V FPGA also applies to the FPGA portion of the Cyclone V SoC as they both use the same FPGA fabric. Additionally, the Cyclone V SoC offers is the ability to power down the FPGA portion of the device while the HPS remains running. This feature is explained in this section.

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