1.3.1. FPGA Power Consumption 1.3.2. FPGA Portion Power Down 1.3.3. FPGA Power Off Step 1: Board Design (Power Rail) Choices 1.3.4. FPGA Power Off Step 2: Quiet FPGA 1.3.5. FPGA Power Off Step 3: Power Off the FPGA 1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration 1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
1.5.1. Power Monitoring and Measurement 1.5.2. Cyclone V SoC Development Kit Power Management ICs 1.5.3. Cyclone V SoC Development Kit Power Monitor Application 1.5.4. LTC LTpower Play Tool 1.5.5. Using the LTC2978A Linux Driver 1.5.6. Power Measurement Results on Cyclone V SoC Development Kit 1.5.7. Document Revision History
1.3. FPGA Power Reduction Methods
The Cyclone V FPGA power consumption reduction techniques are well documented on Altera’s website and in numerous academic and industry documents. Any FPGA power reduction method that applies to the Cyclone V FPGA also applies to the FPGA portion of the Cyclone V SoC as they both use the same FPGA fabric. Additionally, the Cyclone V SoC offers is the ability to power down the FPGA portion of the device while the HPS remains running. This feature is explained in this section.
FPGA Power Consumption
FPGA Portion Power Down
FPGA Power Off Step 1: Board Design (Power Rail) Choices
FPGA Power Off Step 2: Quiet FPGA
FPGA Power Off Step 3: Power Off the FPGA
FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration
FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
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