Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents

1.2.2. Peripherals

In addition to the MPU subsystem, the Cyclone V SoC HPS contains a collection of hardened peripherals and interfaces:

  • 2 x 10/100/1000 Ethernet MACs
  • 2 x USB 2.0 OTG Controllers
  • 2 x UARTs
  • 2 x SPI Masters
  • 2 x SPI Slaves
  • 4 x I2C

The majority of the power consumed by the HPS portion of the SoC device is in the MPU and the SDRAM interface. Two additional peripherals that deserve further consideration when it comes to power savings are USB and Ethernet.