Cyclone V SoC Power Optimization

Download PDF
ID 683713
Date 2/09/2015
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V SoC Power Optimization
1. Cyclone V SoC Power Optimization x
1.1. Power Reduction 1.2. HPS Power Reduction Methods 1.3. FPGA Power Reduction Methods 1.4. Power Optimization Summary 1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit
1.2. HPS Power Reduction Methods x
1.2.1. MPU 1.2.2. Peripherals 1.2.3. HPS Power Reduction Summary
1.2.1. MPU x
1.2.1.1. HPS Method 1: Fit Code in Cache 1.2.1.2. HPS Method 2: Processor Standby Modes and Dynamic Clock Gating 1.2.1.3. HPS Method 3: CPU1 in WFI/WFE or Standby Loop 1.2.1.4. HPS Method 4: Lowering CPU Frequency
1.2.2. Peripherals x
1.2.2.1. HPS Method 5: Energy Efficient Ethernet 1.2.2.2. HPS Method 6: USB Power Management 1.2.2.3. HPS Method 7: Unused Peripherals in Reset
1.3. FPGA Power Reduction Methods x
1.3.1. FPGA Power Consumption 1.3.2. FPGA Portion Power Down 1.3.3. FPGA Power Off Step 1: Board Design (Power Rail) Choices 1.3.4. FPGA Power Off Step 2: Quiet FPGA 1.3.5. FPGA Power Off Step 3: Power Off the FPGA 1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration 1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit x
1.5.1. Power Monitoring and Measurement 1.5.2. Cyclone V SoC Development Kit Power Management ICs 1.5.3. Cyclone V SoC Development Kit Power Monitor Application 1.5.4. LTC LTpower Play Tool 1.5.5. Using the LTC2978A Linux Driver 1.5.6. Power Measurement Results on Cyclone V SoC Development Kit 1.5.7. Document Revision History
1.5.3. Cyclone V SoC Development Kit Power Monitor Application x
1.5.3.1. Starting the Application 1.5.3.2. Windows Instructions 1.5.3.3. Linux Instructions
1.5.4. LTC LTpower Play Tool x
1.5.4.1. Requirements 1.5.4.2. LTC Video Tutorial
1.5.5. Using the LTC2978A Linux Driver x
1.5.5.1. Compiling the Driver 1.5.5.2. Using the Driver
1. Cyclone V SoC Power Optimization

1.5.6. Power Measurement Results on Cyclone V SoC Development Kit

Once you have your preferred power measurement set configured and running, you can take power measurements of the Cyclone V SoC device. The table below shows results across four different boards in four different lab locations.

Table 4.  Linux Idle Power Measurement on Cyclone V SoC Development Kit
Power Rail (V) Board 1 Rev A Dev Kit Measured (W) Board 2 Rev C Dev Kit Measured (W) Board 3 Rev C Dev Kit Measured (W) Board 4 Rev C Dev Kit Measured (W) Average (W)
HPS 1.1 0.390 0.40 0.39 0.39 0.393
HPS 1.5 0.081 0.08 0.08 0.08 0.080
HPS 2.5 0.488 0.62 0.47 0.59 0.542
HPS 3.3 0.106 0.06 0.09 0.08 0.084
FPGA 2.5 0.039 0.03 0.05 0.02 0.035
FPGA 1.5 0.007 0.003 0.007 0.01 0.007
FPGA 1.1 0.059 0.13 0.08 0.15 0.105
Total Power 1.170 1.32 1.17 1.31 1.246

Measurements were taken at room temperature running Linux idle. The FPGA portion of the SoC is programmed with the Golden Hardware Reference Design (GHRD) which is included standard with the development kit.

Because a (3mΩ) sense resistor is used on both the HPS 1.5V and the FPGA 1.5V rails, measurements from the board should be divided by 3 on those rails. The results above show the divided by 3 values.

Figure 8. Sense Resistors

The board revision can be found on the back of the Cyclone V SoC Development Kit board with Rev A being the initial engineering sample version. The latest production version have upgraded to the Enpirion power supply solution.

The results are fairly consistent across the different boards with some minor variance in different rails. Once your equipment is set up, these results can be used to verify your measurement techniques are being done properly.

Level Two Title