Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents HPS Method 1: Fit Code in Cache

Accesses to and from the DDR SDRAM can consume large amounts of power (>=400 mW). Ensuring that your code fits into the 512KB of the L2 Cache can significantly reduce power consumption requirements. The amount of power saved depends upon the interface type (DDR2, DDR3, and LPDDR2) and speed of the interface.