Cyclone V SoC Power Optimization

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ID 683713
Date 2/09/2015
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V SoC Power Optimization
1. Cyclone V SoC Power Optimization x
1.1. Power Reduction 1.2. HPS Power Reduction Methods 1.3. FPGA Power Reduction Methods 1.4. Power Optimization Summary 1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit
1.2. HPS Power Reduction Methods x
1.2.1. MPU 1.2.2. Peripherals 1.2.3. HPS Power Reduction Summary
1.2.1. MPU x
1.2.1.1. HPS Method 1: Fit Code in Cache 1.2.1.2. HPS Method 2: Processor Standby Modes and Dynamic Clock Gating 1.2.1.3. HPS Method 3: CPU1 in WFI/WFE or Standby Loop 1.2.1.4. HPS Method 4: Lowering CPU Frequency
1.2.2. Peripherals x
1.2.2.1. HPS Method 5: Energy Efficient Ethernet 1.2.2.2. HPS Method 6: USB Power Management 1.2.2.3. HPS Method 7: Unused Peripherals in Reset
1.3. FPGA Power Reduction Methods x
1.3.1. FPGA Power Consumption 1.3.2. FPGA Portion Power Down 1.3.3. FPGA Power Off Step 1: Board Design (Power Rail) Choices 1.3.4. FPGA Power Off Step 2: Quiet FPGA 1.3.5. FPGA Power Off Step 3: Power Off the FPGA 1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration 1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit x
1.5.1. Power Monitoring and Measurement 1.5.2. Cyclone V SoC Development Kit Power Management ICs 1.5.3. Cyclone V SoC Development Kit Power Monitor Application 1.5.4. LTC LTpower Play Tool 1.5.5. Using the LTC2978A Linux Driver 1.5.6. Power Measurement Results on Cyclone V SoC Development Kit 1.5.7. Document Revision History
1.5.3. Cyclone V SoC Development Kit Power Monitor Application x
1.5.3.1. Starting the Application 1.5.3.2. Windows Instructions 1.5.3.3. Linux Instructions
1.5.4. LTC LTpower Play Tool x
1.5.4.1. Requirements 1.5.4.2. LTC Video Tutorial
1.5.5. Using the LTC2978A Linux Driver x
1.5.5.1. Compiling the Driver 1.5.5.2. Using the Driver
1. Cyclone V SoC Power Optimization

1.2.1.2. HPS Method 2: Processor Standby Modes and Dynamic Clock Gating

The Cortex-A9 processor can utilize clock-gating logic throughout the MPU subsystem.

Check that the following are enabled/set prior to placing cores in a clock-gated mode:

  1. Enable dynamic clock gating in the processor cores. Use a CP15 (co-processor) assembly command to access the "Power Control Register".
    asm volatile("mcr p15,0,%0,c15,c0,0"::"r"(0x701));
    Note: The code is GCC specific. Similar syntax can be used with other compliers.
  2. Ensure the IRQ controller and SCU can take advantage of clock-gated mode. Both IRQ and SCU are set/controlled in the SCU control register:
    1. Bit 6 disables the IRQ Controller clock when no IRQs are pending
    2. Bit 5 puts the SCU into standby mode when all processors are clock-gated 
    volatile uint32 *scucr = (volatile uint32*) 0xFFFEC000; 
*scucr |= 0x60;
  3. Enable L2 clock-gating and standby mode. In the Power Control register of the L2-310 Cache Controller, ensure that dynamic clock gating and standby mode are both enabled:
    1. Dynamic Clock Gating: Set bit1 of pwr_ctrl register
    2. Standby Mode: Set bit0 of pwr_ctrl register
      volatile uint32 *reg15_power_control = (volatile uint32*) 0xFFFEFF80; 
reg15_power_control |= 0x03;

Please refer to the AMBA Level 2 Cache Controller Technical Reference Manual and Cortex-A9 MPCore Technical Reference Manual for detailed descriptions of the CP15 register, Snoop Control Unit's (SCU's) control register, and the cache controller's power control register.

After ensuring that dynamic clock gating is used within the MPU subsystem, you can put one or both of the Cortex A-9 processor CPUs into clock gating mode by issuing a WFI (wait for interrupt) or WFE (wait for event) assembly instructions. Which one you choose depends on the required system behavior.

Bare-metal design examples illustrating the usage of WFI/WFE and the standby mode (dynamic clock gating) that it enables are included in a companion ZIP file (Power_Optimization.zip). Unzip this file to see two examples. In one of the these designs, one CPU is configured to be in and out of standby mode using the SEV instruction. The other design uses pushbutton IRQs to wake the CPU from the WFI mode.

Note: None of these clock-gating modes activate until one of the CPUs initiates the standby mode with a WFI or WFE call. The wake-up trigger from WFI or WFE mode is well described in ARM's Cortex-A9 documentation. Wake up a core in standby with a running core by issuing a SEV instruction.
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