Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents HPS Method 2: Processor Standby Modes and Dynamic Clock Gating

The Cortex-A9 processor can utilize clock-gating logic throughout the MPU subsystem.

Check that the following are enabled/set prior to placing cores in a clock-gated mode:

  1. Enable dynamic clock gating in the processor cores. Use a CP15 (co-processor) assembly command to access the "Power Control Register".
    asm volatile("mcr p15,0,%0,c15,c0,0"::"r"(0x701));
    Note: The code is GCC specific. Similar syntax can be used with other compliers.
  2. Ensure the IRQ controller and SCU can take advantage of clock-gated mode. Both IRQ and SCU are set/controlled in the SCU control register:
    1. Bit 6 disables the IRQ Controller clock when no IRQs are pending
    2. Bit 5 puts the SCU into standby mode when all processors are clock-gated
    volatile uint32 *scucr = (volatile uint32*) 0xFFFEC000; 
    *scucr |= 0x60;
  3. Enable L2 clock-gating and standby mode. In the Power Control register of the L2-310 Cache Controller, ensure that dynamic clock gating and standby mode are both enabled:
    1. Dynamic Clock Gating: Set bit1 of pwr_ctrl register
    2. Standby Mode: Set bit0 of pwr_ctrl register
      volatile uint32 *reg15_power_control = (volatile uint32*) 0xFFFEFF80; 
      reg15_power_control |= 0x03; 

Please refer to the AMBA Level 2 Cache Controller Technical Reference Manual and Cortex-A9 MPCore Technical Reference Manual for detailed descriptions of the CP15 register, Snoop Control Unit's (SCU's) control register, and the cache controller's power control register.

After ensuring that dynamic clock gating is used within the MPU subsystem, you can put one or both of the Cortex A-9 processor CPUs into clock gating mode by issuing a WFI (wait for interrupt) or WFE (wait for event) assembly instructions. Which one you choose depends on the required system behavior.

Bare-metal design examples illustrating the usage of WFI/WFE and the standby mode (dynamic clock gating) that it enables are included in a companion ZIP file ( Unzip this file to see two examples. In one of the these designs, one CPU is configured to be in and out of standby mode using the SEV instruction. The other design uses pushbutton IRQs to wake the CPU from the WFI mode.

Note: None of these clock-gating modes activate until one of the CPUs initiates the standby mode with a WFI or WFE call. The wake-up trigger from WFI or WFE mode is well described in ARM's Cortex-A9 documentation. Wake up a core in standby with a running core by issuing a SEV instruction.