Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents

1.3.4. FPGA Power Off Step 2: Quiet FPGA

The FPGA must be inactive and connectivity between the HPS and FPGA must be held in reset when a power or configuration/re-configuration event is initiated. These conditions are similar to those you would have when re-configuring or power cycling a discrete FPGA. Ensuring that your design is not issuing transactions over any of the HPS-to-FPGA bridges is the minimum requirement.

One way to do this would be to implement a register-controlled signal in your FPGA design logic that would end all activity and perform an ordered shutdown. Once the ordered shutdown is complete, an ACK bit could be set so the last transaction would be reading that bit. The last transaction would likely be over the lwhps2fpga bridge.

Once your FPGA design is quiet, you must ensure that the bridges between the FPGA and HPS side of the SoC device are disabled. Do this by putting all the bridges in reset. Visit the SoC HPS Address and Register Descriptions page for the Cyclone V and find the brgmodrst register, located at address 0xFFD0501C in the reset manager register section.

Below is how to put each bridge register in reset from within u-boot connected to a Cyclone V SoC Development Kit:

SOCFPGA_CYCLONE5 # mm 0xffd0501c

ffd0501c: 00000000 ? 7

ffd05020: 00000000 ? q

Using u-boot’s mm command and the information on the SoC HPS Address and Register Descriptions page mentioned above, the bridges are placed in reset. By setting a value of 7 (0’b0111) to the brgmodrst register, each bridge is held in reset and it is now safe to power cycle the FPGA side of the SoC.

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