Cyclone V SoC Power Optimization

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ID 683713
Date 2/09/2015
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V SoC Power Optimization
1. Cyclone V SoC Power Optimization x
1.1. Power Reduction 1.2. HPS Power Reduction Methods 1.3. FPGA Power Reduction Methods 1.4. Power Optimization Summary 1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit
1.2. HPS Power Reduction Methods x
1.2.1. MPU 1.2.2. Peripherals 1.2.3. HPS Power Reduction Summary
1.2.1. MPU x
1.2.1.1. HPS Method 1: Fit Code in Cache 1.2.1.2. HPS Method 2: Processor Standby Modes and Dynamic Clock Gating 1.2.1.3. HPS Method 3: CPU1 in WFI/WFE or Standby Loop 1.2.1.4. HPS Method 4: Lowering CPU Frequency
1.2.2. Peripherals x
1.2.2.1. HPS Method 5: Energy Efficient Ethernet 1.2.2.2. HPS Method 6: USB Power Management 1.2.2.3. HPS Method 7: Unused Peripherals in Reset
1.3. FPGA Power Reduction Methods x
1.3.1. FPGA Power Consumption 1.3.2. FPGA Portion Power Down 1.3.3. FPGA Power Off Step 1: Board Design (Power Rail) Choices 1.3.4. FPGA Power Off Step 2: Quiet FPGA 1.3.5. FPGA Power Off Step 3: Power Off the FPGA 1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration 1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit x
1.5.1. Power Monitoring and Measurement 1.5.2. Cyclone V SoC Development Kit Power Management ICs 1.5.3. Cyclone V SoC Development Kit Power Monitor Application 1.5.4. LTC LTpower Play Tool 1.5.5. Using the LTC2978A Linux Driver 1.5.6. Power Measurement Results on Cyclone V SoC Development Kit 1.5.7. Document Revision History
1.5.3. Cyclone V SoC Development Kit Power Monitor Application x
1.5.3.1. Starting the Application 1.5.3.2. Windows Instructions 1.5.3.3. Linux Instructions
1.5.4. LTC LTpower Play Tool x
1.5.4.1. Requirements 1.5.4.2. LTC Video Tutorial
1.5.5. Using the LTC2978A Linux Driver x
1.5.5.1. Compiling the Driver 1.5.5.2. Using the Driver
1. Cyclone V SoC Power Optimization

1.3.4. FPGA Power Off Step 2: Quiet FPGA

The FPGA must be inactive and connectivity between the HPS and FPGA must be held in reset when a power or configuration/re-configuration event is initiated. These conditions are similar to those you would have when re-configuring or power cycling a discrete FPGA. Ensuring that your design is not issuing transactions over any of the HPS-to-FPGA bridges is the minimum requirement.

One way to do this would be to implement a register-controlled signal in your FPGA design logic that would end all activity and perform an ordered shutdown. Once the ordered shutdown is complete, an ACK bit could be set so the last transaction would be reading that bit. The last transaction would likely be over the lwhps2fpga bridge.

Once your FPGA design is quiet, you must ensure that the bridges between the FPGA and HPS side of the SoC device are disabled. Do this by putting all the bridges in reset. Visit the SoC HPS Address and Register Descriptions page for the Cyclone V and find the brgmodrst register, located at address 0xFFD0501C in the reset manager register section.

Below is how to put each bridge register in reset from within u-boot connected to a Cyclone V SoC Development Kit:

SOCFPGA_CYCLONE5 # mm 0xffd0501c

ffd0501c: 00000000 ? 7

ffd05020: 00000000 ? q

Using u-boot’s mm command and the information on the SoC HPS Address and Register Descriptions page mentioned above, the bridges are placed in reset. By setting a value of 7 (0’b0111) to the brgmodrst register, each bridge is held in reset and it is now safe to power cycle the FPGA side of the SoC.

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