1.3.1. FPGA Power Consumption
Because the elements of the HPS are hardened, they generally consume less space and therefore less power than the FPGA portion of the SoC device. Both static and operational power tend to run higher on the FPGA portion than on the HPS portion of the device.
For example, the Altera PowerPlay Early Power Estimator (EPE) was used to examine a high power demand case where a 110KLE Cyclone V SoC ran a Linpack benchmark test on both CPUs in the Cortex-A9 processor operating at 800 MHz with heavily loaded FPGA logic. In this example, 69% of the total power was dynamic power consumed by the FPGA logic, 23% was HPS dynamic plus static power, and the remaining 8% is FPGA static power. Therefore, it is advantageous to be able to power down the FPGA side of the device to remove as much of the FPGA dynamic power as possible when it is not being used.
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