Cyclone V SoC Power Optimization

ID 683713
Date 2/09/2015
Document Table of Contents

1. Cyclone V SoC Power Optimization

"How do I squeeze another 10m W out of my design?” A question that seemingly only plagued mobile handset designers a decade ago is now an important consideration for nearly every embedded designer. Choosing an Altera® SoC FPGA is the first major step in the direction of minimizing power, saving up to 30% or more compared to previous generation 2-chip solutions (processor/DSP + FPGA). Optimizing the design of the power supply itself can also be of major benefit. However, there are additional steps you can take in optimizing the power consumption in a Cyclone®V SoC. This application note discusses methods to minimize power consumption to help meet the power targets for your design.