1.3.2. FPGA Portion Power Down
Altera SoCs have separate power planes for the HPS and FPGA portions of the device. Due to separate power planes, the Cyclone V SoC offers the ability to power down the FPGA when it's not being utilized while the HPS portion remains running. To implement the FPGA power down mode, the board power rails must be designed properly as an initial foundation. Additionally, the FPGA must be inactive with the HPS-to-FPGA bus interfaces held in reset before the FPGA portion is powered down. The FPGA power down is triggered by executing a power off command. As with any device power down mode, there will be some wake-up time to bring the FPGA portion back to life. This time is based on the FPGA configuration time.
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