Intel® Agilex™ Configuration User Guide

ID 683673
Date 7/05/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Designing with the PFL II IP Core for Avalon-ST Single Device Configuration

This section describes the procedures on how to use the PFL II IP core.

To target a MAX® II, MAX® V, or Intel® MAX® 10 device requires the use of Intel® Quartus® Prime Standard Edition whereas targeting a Intel® Agilex™ requires Intel® Quartus® Prime Pro Edition.

The process of creating the Avalon-ST single device configuration design targeting a MAX10/MAX V/MAX II device involves three steps.
  1. Generate the AVST design for the MAX device with the default option address.
  2. Create the Intel® Agilex™ .pof file in setting the appropriate option bits.
  3. Regenerate the Parallel Flash Loader II Intel FPGA IP (PFL II) with the option bits used to generate the Intel® Agilex™ .pof file and recompile the Intel® MAX® 10 design.

You can find an Intel® MAX® 10 system design example that implements the PFL II IP for AVST x32 configuration mode in the installer package of the Intel® Agilex™ F-Series Transceiver-SoC Development Kit.

Figure 26. Process for Using the PFL IP CoreFigure shows the process for using the PFL IP core, using MAX® II as an example.