Intel® Agilex™ Configuration User Guide

ID 683673
Date 7/05/2022
Public

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3.2.7. Serial Flash Memory Layout

Serial flash devices store the configuration data in sections. The first stage boot loader location depends on the selected serial flash memory layout.

Non-HPS Case:

The following diagram illustrates sections of a non-HPS Intel® Agilex™ configuration data mapping in a serial flash device. The non-HPS bitstreams do not include first stage boot loader (FSBL). Refer to Intel® Agilex™ SoC FPGA Bitstream Sections of the HPS Technical Reference Manual for more information about flash memory layout for HPS devices.

Figure 45. Serial Flash Memory Layout Diagram: Non-HPS Case

HPS Case with FPGA First Option:

The following diagram illustrates sections of an HPS Intel® Agilex™ configuration data mapping in a serial flash device and the HPS first stage boot loader (FSBL) location when you select the FPGA First option.
Figure 46. Serial Flash Memory Layout Diagram: HPS Case with FPGA First Option

HPS Case with HPS First Option and Dual Flash:

The following diagram illustrates sections of an HPS Intel® Agilex™ configuration data mapping in a serial flash device when you select the HPS First option.
Figure 47. Serial Flash Memory Layout Diagram: HPS Case with HPS First Option

If you use a third-party programmer to program an .rpd, ensure that the configuration data is stored starting from address 0 of the serial flash device. If you use .jic or .pof files, the Intel® Agilex™ Programmer automatically programs the configuration data starting from address 0 of the serial flash device.

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